fp.isa (13979:1e0c4607ac12) fp.isa (14043:2cbe8d275b08)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 2525 unchanged lines hidden (view full) ---

2534 return decodeVfpRegRegRegOp<VsubS>(
2535 machInst, vd, vn, vm, false);
2536 } else {
2537 return decodeVfpRegRegRegOp<VsubD>(
2538 machInst, vd, vn, vm, true);
2539 }
2540 }
2541 case 0x8:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 2525 unchanged lines hidden (view full) ---

2534 return decodeVfpRegRegRegOp<VsubS>(
2535 machInst, vd, vn, vm, false);
2536 } else {
2537 return decodeVfpRegRegRegOp<VsubD>(
2538 machInst, vd, vn, vm, true);
2539 }
2540 }
2541 case 0x8:
2542 if (machInst.condCode == 0xF) {
2543 const bool op = bits(machInst, 6);
2544 const uint32_t size = bits(machInst, 9, 8);
2545 if (op) {
2546 if (size == 1) {
2547 return new FailUnimplemented("vminnm.f16", machInst);
2548 }
2549 return decodeNeonSizeSingleDouble<VminnmS, VminnmD>(
2550 size, machInst, vd, vn, vm);
2551 } else {
2552 if (size == 1) {
2553 return new FailUnimplemented("vmaxnm.f16", machInst);
2554 }
2555 return decodeNeonSizeSingleDouble<VmaxnmS, VmaxnmD>(
2556 size, machInst, vd, vn, vm);
2557 }
2558 }
2542 if ((opc3 & 0x1) == 0) {
2543 if (single) {
2544 return decodeVfpRegRegRegOp<VdivS>(
2545 machInst, vd, vn, vm, false);
2546 } else {
2547 return decodeVfpRegRegRegOp<VdivD>(
2548 machInst, vd, vn, vm, true);
2549 }

--- 302 unchanged lines hidden --- 		2559 if ((opc3 & 0x1) == 0) {
2560 if (single) {
2561 return decodeVfpRegRegRegOp<VdivS>(
2562 machInst, vd, vn, vm, false);
2563 } else {
2564 return decodeVfpRegRegRegOp<VdivD>(
2565 machInst, vd, vn, vm, true);
2566 }

--- 302 unchanged lines hidden ---