fp.isa (13738:84439021dcf6) | fp.isa (13753:b9671850fdce) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2011, 2016-2019 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 2087 unchanged lines hidden (view full) --- 2096 return new VcvtaFpUIntS(machInst, vdInt, vm); 2097 } 2098 case 0x3: 2099 if (op) { 2100 return new VcvtaFpSIntD(machInst, vdInt, vm); 2101 } else { 2102 return new VcvtaFpUIntD(machInst, vdInt, vm); 2103 } | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2011, 2016-2019 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 2087 unchanged lines hidden (view full) --- 2096 return new VcvtaFpUIntS(machInst, vdInt, vm); 2097 } 2098 case 0x3: 2099 if (op) { 2100 return new VcvtaFpSIntD(machInst, vdInt, vm); 2101 } else { 2102 return new VcvtaFpUIntD(machInst, vdInt, vm); 2103 } |
2104 default: return new Unknown(machInst); |
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2104 } 2105 case 0x1: 2106 switch(size) { 2107 case 0x0: 2108 return new Unknown(machInst); 2109 case 0x1: 2110 return new FailUnimplemented( 2111 "vcvtn.u32.f16", machInst); --- 4 unchanged lines hidden (view full) --- 2116 return new VcvtnFpUIntS(machInst, vdInt, vm); 2117 } 2118 case 0x3: 2119 if (op) { 2120 return new VcvtnFpSIntD(machInst, vdInt, vm); 2121 } else { 2122 return new VcvtnFpUIntD(machInst, vdInt, vm); 2123 } | 2105 } 2106 case 0x1: 2107 switch(size) { 2108 case 0x0: 2109 return new Unknown(machInst); 2110 case 0x1: 2111 return new FailUnimplemented( 2112 "vcvtn.u32.f16", machInst); --- 4 unchanged lines hidden (view full) --- 2117 return new VcvtnFpUIntS(machInst, vdInt, vm); 2118 } 2119 case 0x3: 2120 if (op) { 2121 return new VcvtnFpSIntD(machInst, vdInt, vm); 2122 } else { 2123 return new VcvtnFpUIntD(machInst, vdInt, vm); 2124 } |
2125 default: return new Unknown(machInst); |
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2124 } 2125 case 0x2: 2126 switch(size) { 2127 case 0x0: 2128 return new Unknown(machInst); 2129 case 0x1: 2130 return new FailUnimplemented( 2131 "vcvtp.u32.f16", machInst); --- 4 unchanged lines hidden (view full) --- 2136 return new VcvtpFpUIntS(machInst, vdInt, vm); 2137 } 2138 case 0x3: 2139 if (op) { 2140 return new VcvtpFpSIntD(machInst, vdInt, vm); 2141 } else { 2142 return new VcvtpFpUIntD(machInst, vdInt, vm); 2143 } | 2126 } 2127 case 0x2: 2128 switch(size) { 2129 case 0x0: 2130 return new Unknown(machInst); 2131 case 0x1: 2132 return new FailUnimplemented( 2133 "vcvtp.u32.f16", machInst); --- 4 unchanged lines hidden (view full) --- 2138 return new VcvtpFpUIntS(machInst, vdInt, vm); 2139 } 2140 case 0x3: 2141 if (op) { 2142 return new VcvtpFpSIntD(machInst, vdInt, vm); 2143 } else { 2144 return new VcvtpFpUIntD(machInst, vdInt, vm); 2145 } |
2146 default: return new Unknown(machInst); |
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2144 } 2145 case 0x3: 2146 switch(size) { 2147 case 0x0: 2148 return new Unknown(machInst); 2149 case 0x1: 2150 return new FailUnimplemented( 2151 "vcvtm.u32.f16", machInst); --- 4 unchanged lines hidden (view full) --- 2156 return new VcvtmFpUIntS(machInst, vdInt, vm); 2157 } 2158 case 0x3: 2159 if (op) { 2160 return new VcvtmFpSIntD(machInst, vdInt, vm); 2161 } else { 2162 return new VcvtmFpUIntD(machInst, vdInt, vm); 2163 } | 2147 } 2148 case 0x3: 2149 switch(size) { 2150 case 0x0: 2151 return new Unknown(machInst); 2152 case 0x1: 2153 return new FailUnimplemented( 2154 "vcvtm.u32.f16", machInst); --- 4 unchanged lines hidden (view full) --- 2159 return new VcvtmFpUIntS(machInst, vdInt, vm); 2160 } 2161 case 0x3: 2162 if (op) { 2163 return new VcvtmFpSIntD(machInst, vdInt, vm); 2164 } else { 2165 return new VcvtmFpUIntD(machInst, vdInt, vm); 2166 } |
2167 default: return new Unknown(machInst); |
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2164 } | 2168 } |
2169 default: return new Unknown(machInst); |
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2165 } 2166 } 2167 } else if (b31_b24 && !b23 && b11_b9 && !op3 && b4){ 2168 // VSEL* floating point conditional select 2169 2170 ConditionCode cond; 2171 switch(bits(machInst, 21, 20)) { 2172 case 0x0: cond = COND_EQ; break; --- 624 unchanged lines hidden --- | 2170 } 2171 } 2172 } else if (b31_b24 && !b23 && b11_b9 && !op3 && b4){ 2173 // VSEL* floating point conditional select 2174 2175 ConditionCode cond; 2176 switch(bits(machInst, 21, 20)) { 2177 case 0x0: cond = COND_EQ; break; --- 624 unchanged lines hidden --- |