fp.isa (11671:520509f3e66c) fp.isa (12595:b5a51007feac)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011,2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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125 break;
126 case 0x4: width = 2;
127 break;
128 case 0x5:
129 if ((b & 0x1) == 0) {
130 width = 1;
131 break;
132 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011,2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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125 break;
126 case 0x4: width = 2;
127 break;
128 case 0x5:
129 if ((b & 0x1) == 0) {
130 width = 1;
131 break;
132 }
133 // Fall through on purpose.
133 M5_FALLTHROUGH;
134 default:
135 return new Unknown(machInst);
136 }
137 }
138 assert(width > 0 && width <= 4);
139
140 const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
141 const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);

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399 return new VbitD<uint64_t>(machInst, vd, vn, vm);
400 }
401 case 3:
402 if (q) {
403 return new VbifQ<uint64_t>(machInst, vd, vn, vm);
404 } else {
405 return new VbifD<uint64_t>(machInst, vd, vn, vm);
406 }
134 default:
135 return new Unknown(machInst);
136 }
137 }
138 assert(width > 0 && width <= 4);
139
140 const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
141 const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);

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399 return new VbitD<uint64_t>(machInst, vd, vn, vm);
400 }
401 case 3:
402 if (q) {
403 return new VbifQ<uint64_t>(machInst, vd, vn, vm);
404 } else {
405 return new VbifD<uint64_t>(machInst, vd, vn, vm);
406 }
407 default:
408 M5_UNREACHABLE;
407 }
408 } else {
409 switch (c) {
410 case 0:
411 if (q) {
412 return new VandQ<uint64_t>(machInst, vd, vn, vm);
413 } else {
414 return new VandD<uint64_t>(machInst, vd, vn, vm);

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440 case 3:
441 if (q) {
442 return new VornQ<uint64_t>(
443 machInst, vd, vn, vm);
444 } else {
445 return new VornD<uint64_t>(
446 machInst, vd, vn, vm);
447 }
409 }
410 } else {
411 switch (c) {
412 case 0:
413 if (q) {
414 return new VandQ<uint64_t>(machInst, vd, vn, vm);
415 } else {
416 return new VandD<uint64_t>(machInst, vd, vn, vm);

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442 case 3:
443 if (q) {
444 return new VornQ<uint64_t>(
445 machInst, vd, vn, vm);
446 } else {
447 return new VornD<uint64_t>(
448 machInst, vd, vn, vm);
449 }
450 default:
451 M5_UNREACHABLE;
448 }
449 }
450 }
451 case 0x2:
452 if (b) {
453 if (u) {
454 return decodeNeonUThreeReg<VqsubUD, VqsubUQ>(
455 q, size, machInst, vd, vn, vm);

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1545 if (q)
1546 return new NVnegQFp<float>(machInst, vd, vm);
1547 else
1548 return new NVnegDFp<float>(machInst, vd, vm);
1549 } else {
1550 return decodeNeonSTwoMiscReg<NVnegD, NVnegQ>(
1551 q, size, machInst, vd, vm);
1552 }
452 }
453 }
454 }
455 case 0x2:
456 if (b) {
457 if (u) {
458 return decodeNeonUThreeReg<VqsubUD, VqsubUQ>(
459 q, size, machInst, vd, vn, vm);

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1549 if (q)
1550 return new NVnegQFp<float>(machInst, vd, vm);
1551 else
1552 return new NVnegDFp<float>(machInst, vd, vm);
1553 } else {
1554 return decodeNeonSTwoMiscReg<NVnegD, NVnegQ>(
1555 q, size, machInst, vd, vm);
1556 }
1557 default:
1558 return new Unknown64(machInst);
1553 }
1554 case 0x2:
1555 switch (bits(b, 4, 1)) {
1556 case 0x0:
1557 if (q)
1558 return new NVswpQ<uint64_t>(machInst, vd, vm);
1559 else
1560 return new NVswpD<uint64_t>(machInst, vd, vm);

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1854 true, false, true, offset);
1855 case 0x2:
1856 return new VLdmStm(machInst, rn, vd, single,
1857 true, true, false, offset);
1858 case 0x3:
1859 // If rn == sp, then this is called vpop.
1860 return new VLdmStm(machInst, rn, vd, single,
1861 true, true, true, offset);
1559 }
1560 case 0x2:
1561 switch (bits(b, 4, 1)) {
1562 case 0x0:
1563 if (q)
1564 return new NVswpQ<uint64_t>(machInst, vd, vm);
1565 else
1566 return new NVswpD<uint64_t>(machInst, vd, vm);

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1860 true, false, true, offset);
1861 case 0x2:
1862 return new VLdmStm(machInst, rn, vd, single,
1863 true, true, false, offset);
1864 case 0x3:
1865 // If rn == sp, then this is called vpop.
1866 return new VLdmStm(machInst, rn, vd, single,
1867 true, true, true, offset);
1868 default:
1869 M5_UNREACHABLE;
1862 }
1863 }
1864 case 0x2:
1865 if (bits(opcode, 1, 0) == 0x2) {
1866 // If rn == sp, then this is called vpush.
1867 return new VLdmStm(machInst, rn, vd, single,
1868 false, true, false, offset);
1869 } else if (bits(opcode, 1, 0) == 0x3) {
1870 return new VLdmStm(machInst, rn, vd, single,
1871 false, true, true, offset);
1872 }
1870 }
1871 }
1872 case 0x2:
1873 if (bits(opcode, 1, 0) == 0x2) {
1874 // If rn == sp, then this is called vpush.
1875 return new VLdmStm(machInst, rn, vd, single,
1876 false, true, false, offset);
1877 } else if (bits(opcode, 1, 0) == 0x3) {
1878 return new VLdmStm(machInst, rn, vd, single,
1879 false, true, true, offset);
1880 }
1873 // Fall through on purpose
1881 M5_FALLTHROUGH;
1874 case 0x3:
1875 const bool up = (bits(machInst, 23) == 1);
1876 const uint32_t imm = bits(machInst, 7, 0) << 2;
1877 if (single) {
1878 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
1879 (bits(machInst, 22)));
1880 } else {
1881 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |

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1883 const bool up = (bits(machInst, 23) == 1);
1884 const uint32_t imm = bits(machInst, 7, 0) << 2;
1885 if (single) {
1886 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
1887 (bits(machInst, 22)));
1888 } else {
1889 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |

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