1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Floating Point operate instructions 46// 47 48def template FPAExecute {{ 49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 50 { 51 Fault fault = NoFault; 52 53 %(fp_enable_check)s; 54 55 %(op_decl)s; 56 %(op_rd)s; 57 58 if (%(predicate_test)s) { 59 %(code)s; 60 if (fault == NoFault) { 61 %(op_wb)s; 62 } 63 } 64 65 return fault; 66 } 67}}; 68 69def template FloatDoubleDecode {{ 70 { 71 ArmStaticInst *i = NULL; 72 switch (OPCODE_19 << 1 | OPCODE_7) 73 { 74 case 0: 75 i = (ArmStaticInst *)new %(class_name)sS(machInst); 76 break; 77 case 1: 78 i = (ArmStaticInst *)new %(class_name)sD(machInst); 79 break; 80 case 2: 81 case 3: 82 default: 83 panic("Cannot decode float/double nature of the instruction"); 84 } 85 return i; 86 } 87}}; 88 89// Primary format for float point operate instructions: 90def format FloatOp(code, *flags) {{ 91 orig_code = code 92 93 cblk = code 94 iop = InstObjParams(name, Name, 'PredOp', 95 {"code": cblk, 96 "predicate_test": predicateTest}, 97 flags) 98 header_output = BasicDeclare.subst(iop) 99 decoder_output = BasicConstructor.subst(iop) 100 exec_output = FPAExecute.subst(iop) 101 102 sng_cblk = code 103 sng_iop = InstObjParams(name, Name+'S', 'PredOp', 104 {"code": sng_cblk, 105 "predicate_test": predicateTest}, 106 flags) 107 header_output += BasicDeclare.subst(sng_iop) 108 decoder_output += BasicConstructor.subst(sng_iop) 109 exec_output += FPAExecute.subst(sng_iop) 110 111 dbl_code = re.sub(r'\.sf', '.df', orig_code) 112 113 dbl_cblk = dbl_code 114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 115 {"code": dbl_cblk, 116 "predicate_test": predicateTest}, 117 flags) 118 header_output += BasicDeclare.subst(dbl_iop) 119 decoder_output += BasicConstructor.subst(dbl_iop) 120 exec_output += FPAExecute.subst(dbl_iop) 121 122 decode_block = FloatDoubleDecode.subst(iop) 123}}; 124 125let {{ 126 calcFPCcCode = ''' 127 uint16_t _in, _iz, _ic, _iv; 128 129 _in = %(fReg1)s < %(fReg2)s; 130 _iz = %(fReg1)s == %(fReg2)s; 131 _ic = %(fReg1)s >= %(fReg2)s; 132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 133 134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 135 (CondCodes & 0x0FFFFFFF); 136 ''' 137}}; 138 139def format FloatCmp(fReg1, fReg2, *flags) {{ 140 code = calcFPCcCode % vars() 141 iop = InstObjParams(name, Name, 'PredOp', 142 {"code": code, 143 "predicate_test": predicateTest}, 144 flags) 145 header_output = BasicDeclare.subst(iop) 146 decoder_output = BasicConstructor.subst(iop) 147 decode_block = BasicDecode.subst(iop) 148 exec_output = FPAExecute.subst(iop) 149}}; 150 151def format ExtensionRegLoadStore() {{ 152 decode_block = ''' 153 { 154 const uint32_t opcode = bits(machInst, 24, 20); 155 const uint32_t offset = bits(machInst, 7, 0); 156 const bool single = (bits(machInst, 8) == 0); 157 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 158 RegIndex vd; 159 if (single) { 160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 161 bits(machInst, 22)); 162 } else { 163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 164 (bits(machInst, 22) << 5)); 165 } 166 switch (bits(opcode, 4, 3)) { 167 case 0x0: 168 if (bits(opcode, 4, 1) == 0x2 && 169 !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 170 !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 171 if ((bits(machInst, 7, 4) & 0xd) != 1) { 172 break; 173 } 174 const IntRegIndex rt = 175 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 176 const IntRegIndex rt2 = 177 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 178 const bool op = bits(machInst, 20); 179 uint32_t vm; 180 if (single) { 181 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 182 } else { 183 vm = (bits(machInst, 3, 0) << 1) | 184 (bits(machInst, 5) << 5); 185 } 186 if (op) { 187 return new Vmov2Core2Reg(machInst, rt, rt2, 188 (IntRegIndex)vm); 189 } else { 190 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 191 rt, rt2); 192 } 193 } 194 break; 195 case 0x1: 196 switch (bits(opcode, 1, 0)) { 197 case 0x0: 198 return new VLdmStm(machInst, rn, vd, single, 199 true, false, false, offset); 200 case 0x1: 201 return new VLdmStm(machInst, rn, vd, single, 202 true, false, true, offset); 203 case 0x2: 204 return new VLdmStm(machInst, rn, vd, single, 205 true, true, false, offset); 206 case 0x3: 207 // If rn == sp, then this is called vpop. 208 return new VLdmStm(machInst, rn, vd, single, 209 true, true, true, offset); 210 } 211 case 0x2: 212 if (bits(opcode, 1, 0) == 0x2) { 213 // If rn == sp, then this is called vpush. 214 return new VLdmStm(machInst, rn, vd, single, 215 false, true, false, offset); 216 } else if (bits(opcode, 1, 0) == 0x3) { 217 return new VLdmStm(machInst, rn, vd, single, 218 false, true, true, offset); 219 } 220 // Fall through on purpose 221 case 0x3:
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222 const bool up = (bits(machInst, 23) == 1); 223 const uint32_t imm = bits(machInst, 7, 0) << 2; 224 RegIndex vd; 225 if (single) { 226 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 227 (bits(machInst, 22))); 228 } else { 229 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 230 (bits(machInst, 22) << 5)); 231 } |
232 if (bits(opcode, 1, 0) == 0x0) {
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223 return new WarnUnimplemented("vstr", machInst);
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233 if (single) { 234 if (up) { 235 return new %(vstr_us)s(machInst, vd, rn, up, imm); 236 } else { 237 return new %(vstr_s)s(machInst, vd, rn, up, imm); 238 } 239 } else { 240 if (up) { 241 return new %(vstr_ud)s(machInst, vd, vd + 1, 242 rn, up, imm); 243 } else { 244 return new %(vstr_d)s(machInst, vd, vd + 1, 245 rn, up, imm); 246 } 247 } |
248 } else if (bits(opcode, 1, 0) == 0x1) {
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225 const bool up = (bits(machInst, 23) == 1);
226 const uint32_t imm = bits(machInst, 7, 0) << 2;
227 RegIndex vd;
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249 if (single) {
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229 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
230 (bits(machInst, 22)));
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250 if (up) { 251 return new %(vldr_us)s(machInst, vd, rn, up, imm); 252 } else { 253 return new %(vldr_s)s(machInst, vd, rn, up, imm); 254 } 255 } else {
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237 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
238 (bits(machInst, 22) << 5));
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256 if (up) { 257 return new %(vldr_ud)s(machInst, vd, vd + 1, 258 rn, up, imm); 259 } else { 260 return new %(vldr_d)s(machInst, vd, vd + 1, 261 rn, up, imm); 262 } 263 } 264 } 265 } 266 return new Unknown(machInst); 267 } 268 ''' % { 269 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 270 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 271 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
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255 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False)
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272 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 273 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 274 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 275 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 276 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) |
277 } 278}}; 279 280def format ShortFpTransfer() {{ 281 decode_block = ''' 282 { 283 const uint32_t l = bits(machInst, 20); 284 const uint32_t c = bits(machInst, 8); 285 const uint32_t a = bits(machInst, 23, 21); 286 const uint32_t b = bits(machInst, 6, 5); 287 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 288 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 289 return new Unknown(machInst); 290 } 291 if (l == 0 && c == 0) { 292 if (a == 0) { 293 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 294 bits(machInst, 7); 295 const IntRegIndex rt = 296 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 297 if (bits(machInst, 20) == 1) { 298 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 299 } else { 300 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 301 } 302 } else if (a == 0x7) { 303 const IntRegIndex rt = 304 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 305 uint32_t specReg = bits(machInst, 19, 16); 306 switch (specReg) { 307 case 0: 308 specReg = MISCREG_FPSID; 309 break; 310 case 1: 311 specReg = MISCREG_FPSCR; 312 break; 313 case 8: 314 specReg = MISCREG_FPEXC; 315 break; 316 default: 317 return new Unknown(machInst); 318 } 319 return new Vmsr(machInst, (IntRegIndex)specReg, rt); 320 } 321 } else if (l == 0 && c == 1) { 322 if (bits(a, 2) == 0) { 323 uint32_t vd = (bits(machInst, 7) << 5) | 324 (bits(machInst, 19, 16) << 1); 325 uint32_t index, size; 326 const IntRegIndex rt = 327 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 328 if (bits(machInst, 22) == 1) { 329 size = 8; 330 index = (bits(machInst, 21) << 2) | 331 bits(machInst, 6, 5); 332 } else if (bits(machInst, 5) == 1) { 333 size = 16; 334 index = (bits(machInst, 21) << 1) | 335 bits(machInst, 6); 336 } else if (bits(machInst, 6) == 0) { 337 size = 32; 338 index = bits(machInst, 21); 339 } else { 340 return new Unknown(machInst); 341 } 342 if (index >= (32 / size)) { 343 index -= (32 / size); 344 vd++; 345 } 346 switch (size) { 347 case 8: 348 return new VmovCoreRegB(machInst, (IntRegIndex)vd, 349 rt, index); 350 case 16: 351 return new VmovCoreRegH(machInst, (IntRegIndex)vd, 352 rt, index); 353 case 32: 354 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 355 } 356 } else if (bits(b, 1) == 0) { 357 // A8-594 358 return new WarnUnimplemented("vdup", machInst); 359 } 360 } else if (l == 1 && c == 0) { 361 if (a == 0) { 362 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 363 bits(machInst, 7); 364 const IntRegIndex rt = 365 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 366 if (bits(machInst, 20) == 1) { 367 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 368 } else { 369 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 370 } 371 } else if (a == 7) { 372 const IntRegIndex rt = 373 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 374 uint32_t specReg = bits(machInst, 19, 16); 375 switch (specReg) { 376 case 0: 377 specReg = MISCREG_FPSID; 378 break; 379 case 1: 380 specReg = MISCREG_FPSCR; 381 break; 382 case 6: 383 specReg = MISCREG_MVFR1; 384 break; 385 case 7: 386 specReg = MISCREG_MVFR0; 387 break; 388 case 8: 389 specReg = MISCREG_FPEXC; 390 break; 391 default: 392 return new Unknown(machInst); 393 } 394 return new Vmrs(machInst, rt, (IntRegIndex)specReg); 395 } 396 } else { 397 uint32_t vd = (bits(machInst, 7) << 5) | 398 (bits(machInst, 19, 16) << 1); 399 uint32_t index, size; 400 const IntRegIndex rt = 401 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 402 const bool u = (bits(machInst, 23) == 1); 403 if (bits(machInst, 22) == 1) { 404 size = 8; 405 index = (bits(machInst, 21) << 2) | 406 bits(machInst, 6, 5); 407 } else if (bits(machInst, 5) == 1) { 408 size = 16; 409 index = (bits(machInst, 21) << 1) | 410 bits(machInst, 6); 411 } else if (bits(machInst, 6) == 0 && !u) { 412 size = 32; 413 index = bits(machInst, 21); 414 } else { 415 return new Unknown(machInst); 416 } 417 if (index >= (32 / size)) { 418 index -= (32 / size); 419 vd++; 420 } 421 switch (size) { 422 case 8: 423 if (u) { 424 return new VmovRegCoreUB(machInst, rt, 425 (IntRegIndex)vd, index); 426 } else { 427 return new VmovRegCoreSB(machInst, rt, 428 (IntRegIndex)vd, index); 429 } 430 case 16: 431 if (u) { 432 return new VmovRegCoreUH(machInst, rt, 433 (IntRegIndex)vd, index); 434 } else { 435 return new VmovRegCoreSH(machInst, rt, 436 (IntRegIndex)vd, index); 437 } 438 case 32: 439 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 440 } 441 } 442 return new Unknown(machInst); 443 } 444 ''' 445}};
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