1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating
--- 467 unchanged lines hidden (view full) ---
476 decoder_output = ''' 477 StaticInstPtr 478 decodeVfpData(ExtMachInst machInst) 479 { 480 const uint32_t opc1 = bits(machInst, 23, 20); 481 const uint32_t opc2 = bits(machInst, 19, 16); 482 const uint32_t opc3 = bits(machInst, 7, 6); 483 //const uint32_t opc4 = bits(machInst, 3, 0);
|
484 const bool single = (bits(machInst, 8) == 0); 485 IntRegIndex vd; 486 IntRegIndex vm; 487 IntRegIndex vn; 488 if (single) { 489 vd = (IntRegIndex)(bits(machInst, 22) | 490 (bits(machInst, 15, 12) << 1)); 491 vm = (IntRegIndex)(bits(machInst, 5) | 492 (bits(machInst, 3, 0) << 1)); 493 vn = (IntRegIndex)(bits(machInst, 7) | 494 (bits(machInst, 19, 16) << 1)); 495 } else { 496 vd = (IntRegIndex)((bits(machInst, 22) << 5) | 497 (bits(machInst, 15, 12) << 1)); 498 vm = (IntRegIndex)((bits(machInst, 5) << 5) | 499 (bits(machInst, 3, 0) << 1)); 500 vn = (IntRegIndex)((bits(machInst, 7) << 5) | 501 (bits(machInst, 19, 16) << 1)); 502 } |
503 switch (opc1 & 0xb /* 1011 */) { 504 case 0x0: 505 if (bits(machInst, 6) == 0) {
|
487 uint32_t vd;
488 uint32_t vm;
489 uint32_t vn;
490 if (bits(machInst, 8) == 0) {
491 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
492 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
493 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
494 return new VmlaS(machInst, (IntRegIndex)vd,
495 (IntRegIndex)vn, (IntRegIndex)vm);
|
506 if (single) { 507 return new VmlaS(machInst, vd, vn, vm); |
508 } else {
|
497 vd = (bits(machInst, 22) << 5) |
498 (bits(machInst, 15, 12) << 1);
499 vm = (bits(machInst, 5) << 5) |
500 (bits(machInst, 3, 0) << 1);
501 vn = (bits(machInst, 7) << 5) |
502 (bits(machInst, 19, 16) << 1);
503 return new VmlaD(machInst, (IntRegIndex)vd,
504 (IntRegIndex)vn, (IntRegIndex)vm);
|
509 return new VmlaD(machInst, vd, vn, vm); |
510 } 511 } else {
|
507 uint32_t vd;
508 uint32_t vm;
509 uint32_t vn;
510 if (bits(machInst, 8) == 0) {
511 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
512 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
513 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
514 return new VmlsS(machInst, (IntRegIndex)vd,
515 (IntRegIndex)vn, (IntRegIndex)vm);
|
512 if (single) { 513 return new VmlsS(machInst, vd, vn, vm); |
514 } else {
|
517 vd = (bits(machInst, 22) << 5) |
518 (bits(machInst, 15, 12) << 1);
519 vm = (bits(machInst, 5) << 5) |
520 (bits(machInst, 3, 0) << 1);
521 vn = (bits(machInst, 7) << 5) |
522 (bits(machInst, 19, 16) << 1);
523 return new VmlsD(machInst, (IntRegIndex)vd,
524 (IntRegIndex)vn, (IntRegIndex)vm);
|
515 return new VmlsD(machInst, vd, vn, vm); |
516 } 517 } 518 case 0x1: 519 if (bits(machInst, 6) == 1) {
|
529 uint32_t vd;
530 uint32_t vm;
531 uint32_t vn;
532 if (bits(machInst, 8) == 0) {
533 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
534 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
535 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
536 return new VnmlaS(machInst, (IntRegIndex)vd,
537 (IntRegIndex)vn, (IntRegIndex)vm);
|
520 if (single) { 521 return new VnmlaS(machInst, vd, vn, vm); |
522 } else {
|
539 vd = (bits(machInst, 22) << 5) |
540 (bits(machInst, 15, 12) << 1);
541 vm = (bits(machInst, 5) << 5) |
542 (bits(machInst, 3, 0) << 1);
543 vn = (bits(machInst, 7) << 5) |
544 (bits(machInst, 19, 16) << 1);
545 return new VnmlaD(machInst, (IntRegIndex)vd,
546 (IntRegIndex)vn, (IntRegIndex)vm);
|
523 return new VnmlaD(machInst, vd, vn, vm); |
524 } 525 } else {
|
549 uint32_t vd;
550 uint32_t vm;
551 uint32_t vn;
552 if (bits(machInst, 8) == 0) {
553 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
554 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
555 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
556 return new VnmlsS(machInst, (IntRegIndex)vd,
557 (IntRegIndex)vn, (IntRegIndex)vm);
|
526 if (single) { 527 return new VnmlsS(machInst, vd, vn, vm); |
528 } else {
|
559 vd = (bits(machInst, 22) << 5) |
560 (bits(machInst, 15, 12) << 1);
561 vm = (bits(machInst, 5) << 5) |
562 (bits(machInst, 3, 0) << 1);
563 vn = (bits(machInst, 7) << 5) |
564 (bits(machInst, 19, 16) << 1);
565 return new VnmlsD(machInst, (IntRegIndex)vd,
566 (IntRegIndex)vn, (IntRegIndex)vm);
|
529 return new VnmlsD(machInst, vd, vn, vm); |
530 } 531 } 532 case 0x2: 533 if ((opc3 & 0x1) == 0) {
|
571 uint32_t vd;
572 uint32_t vm;
573 uint32_t vn;
574 if (bits(machInst, 8) == 0) {
575 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
576 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
577 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
578 return new VmulS(machInst, (IntRegIndex)vd,
579 (IntRegIndex)vn, (IntRegIndex)vm);
|
534 if (single) { 535 return new VmulS(machInst, vd, vn, vm); |
536 } else {
|
581 vd = (bits(machInst, 22) << 5) |
582 (bits(machInst, 15, 12) << 1);
583 vm = (bits(machInst, 5) << 5) |
584 (bits(machInst, 3, 0) << 1);
585 vn = (bits(machInst, 7) << 5) |
586 (bits(machInst, 19, 16) << 1);
587 return new VmulD(machInst, (IntRegIndex)vd,
588 (IntRegIndex)vn, (IntRegIndex)vm);
|
537 return new VmulD(machInst, vd, vn, vm); |
538 } 539 } else {
|
591 uint32_t vd;
592 uint32_t vm;
593 uint32_t vn;
594 if (bits(machInst, 8) == 0) {
595 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
596 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
597 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
598 return new VnmulS(machInst, (IntRegIndex)vd,
599 (IntRegIndex)vn, (IntRegIndex)vm);
|
540 if (single) { 541 return new VnmulS(machInst, vd, vn, vm); |
542 } else {
|
601 vd = (bits(machInst, 22) << 5) |
602 (bits(machInst, 15, 12) << 1);
603 vm = (bits(machInst, 5) << 5) |
604 (bits(machInst, 3, 0) << 1);
605 vn = (bits(machInst, 7) << 5) |
606 (bits(machInst, 19, 16) << 1);
607 return new VnmulD(machInst, (IntRegIndex)vd,
608 (IntRegIndex)vn, (IntRegIndex)vm);
|
543 return new VnmulD(machInst, vd, vn, vm); |
544 } 545 } 546 case 0x3: 547 if ((opc3 & 0x1) == 0) {
|
613 uint32_t vd;
614 uint32_t vm;
615 uint32_t vn;
616 if (bits(machInst, 8) == 0) {
617 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
618 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
619 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
620 return new VaddS(machInst, (IntRegIndex)vd,
621 (IntRegIndex)vn, (IntRegIndex)vm);
|
548 if (single) { 549 return new VaddS(machInst, vd, vn, vm); |
550 } else {
|
623 vd = (bits(machInst, 22) << 5) |
624 (bits(machInst, 15, 12) << 1);
625 vm = (bits(machInst, 5) << 5) |
626 (bits(machInst, 3, 0) << 1);
627 vn = (bits(machInst, 7) << 5) |
628 (bits(machInst, 19, 16) << 1);
629 return new VaddD(machInst, (IntRegIndex)vd,
630 (IntRegIndex)vn, (IntRegIndex)vm);
|
551 return new VaddD(machInst, vd, vn, vm); |
552 } 553 } else {
|
633 uint32_t vd;
634 uint32_t vm;
635 uint32_t vn;
636 if (bits(machInst, 8) == 0) {
637 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
638 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
639 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
640 return new VsubS(machInst, (IntRegIndex)vd,
641 (IntRegIndex)vn, (IntRegIndex)vm);
|
554 if (single) { 555 return new VsubS(machInst, vd, vn, vm); |
556 } else {
|
643 vd = (bits(machInst, 22) << 5) |
644 (bits(machInst, 15, 12) << 1);
645 vm = (bits(machInst, 5) << 5) |
646 (bits(machInst, 3, 0) << 1);
647 vn = (bits(machInst, 7) << 5) |
648 (bits(machInst, 19, 16) << 1);
649 return new VsubD(machInst, (IntRegIndex)vd,
650 (IntRegIndex)vn, (IntRegIndex)vm);
|
557 return new VsubD(machInst, vd, vn, vm); |
558 } 559 } 560 case 0x8: 561 if ((opc3 & 0x1) == 0) {
|
655 uint32_t vd;
656 uint32_t vm;
657 uint32_t vn;
658 if (bits(machInst, 8) == 0) {
659 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
660 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
661 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
662 return new VdivS(machInst, (IntRegIndex)vd,
663 (IntRegIndex)vn, (IntRegIndex)vm);
|
562 if (single) { 563 return new VdivS(machInst, vd, vn, vm); |
564 } else {
|
665 vd = (bits(machInst, 22) << 5) |
666 (bits(machInst, 15, 12) << 1);
667 vm = (bits(machInst, 5) << 5) |
668 (bits(machInst, 3, 0) << 1);
669 vn = (bits(machInst, 7) << 5) |
670 (bits(machInst, 19, 16) << 1);
671 return new VdivD(machInst, (IntRegIndex)vd,
672 (IntRegIndex)vn, (IntRegIndex)vm);
|
565 return new VdivD(machInst, vd, vn, vm); |
566 } 567 } 568 break; 569 case 0xb: 570 if ((opc3 & 0x1) == 0) {
|
678 uint32_t vd;
|
571 const uint32_t baseImm = 572 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
|
681 if (bits(machInst, 8) == 0) {
682 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
573 if (single) { |
574 uint32_t imm = vfp_modified_imm(baseImm, false);
|
684 return new VmovImmS(machInst, (IntRegIndex)vd, imm);
|
575 return new VmovImmS(machInst, vd, imm); |
576 } else {
|
686 vd = (bits(machInst, 22) << 5) |
687 (bits(machInst, 15, 12) << 1);
|
577 uint64_t imm = vfp_modified_imm(baseImm, true);
|
689 return new VmovImmD(machInst, (IntRegIndex)vd, imm);
|
578 return new VmovImmD(machInst, vd, imm); |
579 } 580 } 581 switch (opc2) { 582 case 0x0: 583 if (opc3 == 1) {
|
695 uint32_t vd;
696 uint32_t vm;
697 if (bits(machInst, 8) == 0) {
698 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
699 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
700 return new VmovRegS(machInst,
701 (IntRegIndex)vd, (IntRegIndex)vm);
|
584 if (single) { 585 return new VmovRegS(machInst, vd, vm); |
586 } else {
|
703 vd = (bits(machInst, 22) << 5) |
704 (bits(machInst, 15, 12) << 1);
705 vm = (bits(machInst, 5) << 5) |
706 (bits(machInst, 3, 0) << 1);
707 return new VmovRegD(machInst,
708 (IntRegIndex)vd, (IntRegIndex)vm);
|
587 return new VmovRegD(machInst, vd, vm); |
588 } 589 } else {
|
711 uint32_t vd;
712 uint32_t vm;
713 if (bits(machInst, 8) == 0) {
714 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
715 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
716 return new VabsS(machInst,
717 (IntRegIndex)vd, (IntRegIndex)vm);
|
590 if (single) { 591 return new VabsS(machInst, vd, vm); |
592 } else {
|
719 vd = (bits(machInst, 22) << 5) |
720 (bits(machInst, 15, 12) << 1);
721 vm = (bits(machInst, 5) << 5) |
722 (bits(machInst, 3, 0) << 1);
723 return new VabsD(machInst,
724 (IntRegIndex)vd, (IntRegIndex)vm);
|
593 return new VabsD(machInst, vd, vm); |
594 } 595 } 596 case 0x1: 597 if (opc3 == 1) {
|
729 uint32_t vd;
730 uint32_t vm;
731 if (bits(machInst, 8) == 0) {
732 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
733 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
734 return new VnegS(machInst,
735 (IntRegIndex)vd, (IntRegIndex)vm);
|
598 if (single) { 599 return new VnegS(machInst, vd, vm); |
600 } else {
|
737 vd = (bits(machInst, 22) << 5) |
738 (bits(machInst, 15, 12) << 1);
739 vm = (bits(machInst, 5) << 5) |
740 (bits(machInst, 3, 0) << 1);
741 return new VnegD(machInst,
742 (IntRegIndex)vd, (IntRegIndex)vm);
|
601 return new VnegD(machInst, vd, vm); |
602 } 603 } else {
|
745 uint32_t vd;
746 uint32_t vm;
747 if (bits(machInst, 8) == 0) {
748 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
749 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
750 return new VsqrtS(machInst,
751 (IntRegIndex)vd, (IntRegIndex)vm);
|
604 if (single) { 605 return new VsqrtS(machInst, vd, vm); |
606 } else {
|
753 vd = (bits(machInst, 22) << 5) |
754 (bits(machInst, 15, 12) << 1);
755 vm = (bits(machInst, 5) << 5) |
756 (bits(machInst, 3, 0) << 1);
757 return new VsqrtD(machInst,
758 (IntRegIndex)vd, (IntRegIndex)vm);
|
607 return new VsqrtD(machInst, vd, vm); |
608 } 609 } 610 case 0x2: 611 case 0x3: 612 // Between half and single precision. 613 return new WarnUnimplemented("vcvtb, vcvtt", machInst); 614 case 0x4: 615 case 0x5:
--- 35 unchanged lines hidden --- |