1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 151 unchanged lines hidden (view full) --- 160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 161 bits(machInst, 22)); 162 } else { 163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 164 (bits(machInst, 22) << 5)); 165 } 166 switch (bits(opcode, 4, 3)) { 167 case 0x0: |
168 if (bits(opcode, 4, 1) == 0x2 && 169 !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 170 !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 171 if ((bits(machInst, 7, 4) & 0xd) != 1) { 172 break; 173 } 174 const IntRegIndex rt = 175 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 176 const IntRegIndex rt2 = 177 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 178 const bool op = bits(machInst, 20); 179 uint32_t vm; 180 if (bits(machInst, 8) == 0) { 181 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 182 } else { 183 vm = (bits(machInst, 3, 0) << 1) | 184 (bits(machInst, 5) << 5); 185 } 186 if (op) { 187 return new Vmov2Core2Reg(machInst, rt, rt2, 188 (IntRegIndex)vm); 189 } else { 190 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 191 rt, rt2); 192 } |
193 } 194 break; 195 case 0x1: 196 switch (bits(opcode, 1, 0)) { 197 case 0x0: 198 return new VLdmStm(machInst, rn, vd, single, 199 true, false, false, offset); 200 case 0x1: --- 37 unchanged lines hidden (view full) --- 238 const uint32_t a = bits(machInst, 23, 21); 239 const uint32_t b = bits(machInst, 6, 5); 240 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 241 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 242 return new Unknown(machInst); 243 } 244 if (l == 0 && c == 0) { 245 if (a == 0) { |
246 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 247 bits(machInst, 7); 248 const IntRegIndex rt = 249 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 250 if (bits(machInst, 20) == 1) { 251 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 252 } else { 253 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 254 } |
255 } else if (a == 0x7) { 256 const IntRegIndex rt = 257 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 258 uint32_t specReg = bits(machInst, 19, 16); 259 switch (specReg) { 260 case 0: 261 specReg = MISCREG_FPSID; 262 break; --- 5 unchanged lines hidden (view full) --- 268 break; 269 default: 270 return new Unknown(machInst); 271 } 272 return new Vmsr(machInst, (IntRegIndex)specReg, rt); 273 } 274 } else if (l == 0 && c == 1) { 275 if (bits(a, 2) == 0) { |
276 uint32_t vd = (bits(machInst, 7) << 5) | 277 (bits(machInst, 19, 16) << 1); 278 uint32_t index, size; 279 const IntRegIndex rt = 280 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 281 if (bits(machInst, 22) == 1) { 282 size = 8; 283 index = (bits(machInst, 21) << 2) | 284 bits(machInst, 6, 5); 285 } else if (bits(machInst, 5) == 1) { 286 size = 16; 287 index = (bits(machInst, 21) << 1) | 288 bits(machInst, 6); 289 } else if (bits(machInst, 6) == 0) { 290 size = 32; 291 index = bits(machInst, 21); 292 } else { 293 return new Unknown(machInst); 294 } 295 if (index >= (32 / size)) { 296 index -= (32 / size); 297 vd++; 298 } 299 switch (size) { 300 case 8: 301 return new VmovCoreRegB(machInst, (IntRegIndex)vd, 302 rt, index); 303 case 16: 304 return new VmovCoreRegH(machInst, (IntRegIndex)vd, 305 rt, index); 306 case 32: 307 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 308 } |
309 } else if (bits(b, 1) == 0) { 310 // A8-594 311 return new WarnUnimplemented("vdup", machInst); 312 } 313 } else if (l == 1 && c == 0) { 314 if (a == 0) { |
315 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 316 bits(machInst, 7); 317 const IntRegIndex rt = 318 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 319 if (bits(machInst, 20) == 1) { 320 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 321 } else { 322 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 323 } |
324 } else if (a == 7) { 325 const IntRegIndex rt = 326 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 327 uint32_t specReg = bits(machInst, 19, 16); 328 switch (specReg) { 329 case 0: 330 specReg = MISCREG_FPSID; 331 break; --- 10 unchanged lines hidden (view full) --- 342 specReg = MISCREG_FPEXC; 343 break; 344 default: 345 return new Unknown(machInst); 346 } 347 return new Vmrs(machInst, rt, (IntRegIndex)specReg); 348 } 349 } else { |
350 uint32_t vd = (bits(machInst, 7) << 5) | 351 (bits(machInst, 19, 16) << 1); 352 uint32_t index, size; 353 const IntRegIndex rt = 354 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 355 const bool u = (bits(machInst, 23) == 1); 356 if (bits(machInst, 22) == 1) { 357 size = 8; 358 index = (bits(machInst, 21) << 2) | 359 bits(machInst, 6, 5); 360 } else if (bits(machInst, 5) == 1) { 361 size = 16; 362 index = (bits(machInst, 21) << 1) | 363 bits(machInst, 6); 364 } else if (bits(machInst, 6) == 0 && !u) { 365 size = 32; 366 index = bits(machInst, 21); 367 } else { 368 return new Unknown(machInst); 369 } 370 if (index >= (32 / size)) { 371 index -= (32 / size); 372 vd++; 373 } 374 switch (size) { 375 case 8: 376 if (u) { 377 return new VmovRegCoreUB(machInst, rt, 378 (IntRegIndex)vd, index); 379 } else { 380 return new VmovRegCoreSB(machInst, rt, 381 (IntRegIndex)vd, index); 382 } 383 case 16: 384 if (u) { 385 return new VmovRegCoreUH(machInst, rt, 386 (IntRegIndex)vd, index); 387 } else { 388 return new VmovRegCoreSH(machInst, rt, 389 (IntRegIndex)vd, index); 390 } 391 case 32: 392 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 393 } |
394 } 395 return new Unknown(machInst); 396 } 397 ''' 398}}; |