1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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336 }
337 '''
338
339 decoder_output += '''
340 static StaticInstPtr
341 decodeNeonThreeRegistersSameLength(ExtMachInst machInst)
342 {
343 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
344 const uint32_t a = bits(machInst, 11, 8);
345 const bool b = bits(machInst, 4);
346 const uint32_t c = bits(machInst, 21, 20);
344 const uint32_t opc = bits(machInst, 11, 8);
345 const bool o1 = bits(machInst, 4);
346 const uint32_t size = bits(machInst, 21, 20);
347 const IntRegIndex vd =
348 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
349 (bits(machInst, 22) << 4)));
350 const IntRegIndex vn =
351 (IntRegIndex)(2 * (bits(machInst, 19, 16) |
352 (bits(machInst, 7) << 4)));
353 const IntRegIndex vm =
354 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
355 (bits(machInst, 5) << 4)));
356 const unsigned size = bits(machInst, 21, 20);
356 const bool q = bits(machInst, 6);
357 if (q && ((vd & 0x1) || (vn & 0x1) || (vm & 0x1)))
358 return new Unknown(machInst);
360 switch (a) {
359 switch (opc) {
360 case 0x0:
362 if (b) {
361 if (o1) {
362 if (u) {
363 return decodeNeonUThreeReg<VqaddUD, VqaddUQ>(
364 q, size, machInst, vd, vn, vm);
365 } else {
366 return decodeNeonSThreeReg<VqaddSD, VqaddSQ>(
367 q, size, machInst, vd, vn, vm);
368 }
369 } else {
370 if (size == 3)
371 return new Unknown(machInst);
372 return decodeNeonUSThreeReg<VhaddD, VhaddQ>(
373 q, u, size, machInst, vd, vn, vm);
374 }
375 case 0x1:
377 if (!b) {
376 if (!o1) {
377 return decodeNeonUSThreeReg<VrhaddD, VrhaddQ>(
378 q, u, size, machInst, vd, vn, vm);
379 } else {
380 if (u) {
382 switch (c) {
381 switch (size) {
382 case 0:
383 if (q) {
384 return new VeorQ<uint64_t>(machInst, vd, vn, vm);
385 } else {
386 return new VeorD<uint64_t>(machInst, vd, vn, vm);
387 }
388 case 1:
389 if (q) {

--- 12 unchanged lines hidden (view full) ---

402 return new VbifQ<uint64_t>(machInst, vd, vn, vm);
403 } else {
404 return new VbifD<uint64_t>(machInst, vd, vn, vm);
405 }
406 default:
407 M5_UNREACHABLE;
408 }
409 } else {
411 switch (c) {
410 switch (size) {
411 case 0:
412 if (q) {
413 return new VandQ<uint64_t>(machInst, vd, vn, vm);
414 } else {
415 return new VandD<uint64_t>(machInst, vd, vn, vm);
416 }
417 case 1:
418 if (q) {

--- 28 unchanged lines hidden (view full) ---

447 machInst, vd, vn, vm);
448 }
449 default:
450 M5_UNREACHABLE;
451 }
452 }
453 }
454 case 0x2:
456 if (b) {
455 if (o1) {
456 if (u) {
457 return decodeNeonUThreeReg<VqsubUD, VqsubUQ>(
458 q, size, machInst, vd, vn, vm);
459 } else {
460 return decodeNeonSThreeReg<VqsubSD, VqsubSQ>(
461 q, size, machInst, vd, vn, vm);
462 }
463 } else {
464 if (size == 3)
465 return new Unknown(machInst);
466 return decodeNeonUSThreeReg<VhsubD, VhsubQ>(
467 q, u, size, machInst, vd, vn, vm);
468 }
469 case 0x3:
471 if (b) {
470 if (o1) {
471 return decodeNeonUSThreeReg<VcgeD, VcgeQ>(
472 q, u, size, machInst, vd, vn, vm);
473 } else {
474 return decodeNeonUSThreeReg<VcgtD, VcgtQ>(
475 q, u, size, machInst, vd, vn, vm);
476 }
477 case 0x4:
479 if (b) {
478 if (o1) {
479 if (u) {
480 return decodeNeonUThreeReg<VqshlUD, VqshlUQ>(
481 q, size, machInst, vd, vm, vn);
482 } else {
483 return decodeNeonSThreeReg<VqshlSD, VqshlSQ>(
484 q, size, machInst, vd, vm, vn);
485 }
486 } else {
487 return decodeNeonUSThreeReg<VshlD, VshlQ>(
488 q, u, size, machInst, vd, vm, vn);
489 }
490 case 0x5:
492 if (b) {
491 if (o1) {
492 if (u) {
493 return decodeNeonUThreeReg<VqrshlUD, VqrshlUQ>(
494 q, size, machInst, vd, vm, vn);
495 } else {
496 return decodeNeonSThreeReg<VqrshlSD, VqrshlSQ>(
497 q, size, machInst, vd, vm, vn);
498 }
499 } else {
500 return decodeNeonUSThreeReg<VrshlD, VrshlQ>(
501 q, u, size, machInst, vd, vm, vn);
502 }
503 case 0x6:
505 if (b) {
504 if (o1) {
505 return decodeNeonUSThreeReg<VminD, VminQ>(
506 q, u, size, machInst, vd, vn, vm);
507 } else {
508 return decodeNeonUSThreeReg<VmaxD, VmaxQ>(
509 q, u, size, machInst, vd, vn, vm);
510 }
511 case 0x7:
513 if (b) {
512 if (o1) {
513 return decodeNeonUSThreeReg<VabaD, VabaQ>(
514 q, u, size, machInst, vd, vn, vm);
515 } else {
516 if (bits(machInst, 23) == 1) {
517 if (q) {
518 return new Unknown(machInst);
519 } else {
520 return decodeNeonUSThreeUSReg<Vabdl>(
521 u, size, machInst, vd, vn, vm);
522 }
523 } else {
524 return decodeNeonUSThreeReg<VabdD, VabdQ>(
525 q, u, size, machInst, vd, vn, vm);
526 }
527 }
528 case 0x8:
530 if (b) {
529 if (o1) {
530 if (u) {
531 return decodeNeonUThreeReg<VceqD, VceqQ>(
532 q, size, machInst, vd, vn, vm);
533 } else {
534 return decodeNeonUThreeReg<VtstD, VtstQ>(
535 q, size, machInst, vd, vn, vm);
536 }
537 } else {
538 if (u) {
539 return decodeNeonUThreeReg<NVsubD, NVsubQ>(
540 q, size, machInst, vd, vn, vm);
541 } else {
542 return decodeNeonUThreeReg<NVaddD, NVaddQ>(
543 q, size, machInst, vd, vn, vm);
544 }
545 }
546 case 0x9:
548 if (b) {
547 if (o1) {
548 if (u) {
549 return decodeNeonUThreeReg<NVmulpD, NVmulpQ>(
550 q, size, machInst, vd, vn, vm);
551 } else {
552 return decodeNeonSThreeReg<NVmulD, NVmulQ>(
553 q, size, machInst, vd, vn, vm);
554 }
555 } else {
556 if (u) {
557 return decodeNeonUSThreeReg<NVmlsD, NVmlsQ>(
558 q, u, size, machInst, vd, vn, vm);
559 } else {
560 return decodeNeonUSThreeReg<NVmlaD, NVmlaQ>(
561 q, u, size, machInst, vd, vn, vm);
562 }
563 }
564 case 0xa:
565 if (q)
566 return new Unknown(machInst);
568 if (b) {
567 if (o1) {
568 return decodeNeonUSThreeUSReg<VpminD>(
569 u, size, machInst, vd, vn, vm);
570 } else {
571 return decodeNeonUSThreeUSReg<VpmaxD>(
572 u, size, machInst, vd, vn, vm);
573 }
574 case 0xb:
576 if (b) {
575 if (o1) {
576 if (u || q) {
577 return new Unknown(machInst);
578 } else {
579 return decodeNeonUThreeUSReg<NVpaddD>(
580 size, machInst, vd, vn, vm);
581 }
582 } else {
583 if (u) {
584 return decodeNeonSThreeSReg<VqrdmulhD, VqrdmulhQ>(
585 q, size, machInst, vd, vn, vm);
586 } else {
587 return decodeNeonSThreeSReg<VqdmulhD, VqdmulhQ>(
588 q, size, machInst, vd, vn, vm);
589 }
590 }
591 case 0xc:
593 if (b) {
592 if (o1) {
593 if (!u) {
595 if (bits(c, 1) == 0) {
594 if (bits(size, 1) == 0) {
595 if (q) {
596 return new NVfmaQFp<float>(machInst, vd, vn, vm);
597 } else {
598 return new NVfmaDFp<float>(machInst, vd, vn, vm);
599 }
600 } else {
601 if (q) {
602 return new NVfmsQFp<float>(machInst, vd, vn, vm);
603 } else {
604 return new NVfmsDFp<float>(machInst, vd, vn, vm);
605 }
606 }
607 }
608 } else {
609 if (u) {
611 switch (c) {
610 switch (size) {
611 case 0x0:
612 return new SHA256H(machInst, vd, vn, vm);
613 case 0x1:
614 return new SHA256H2(machInst, vd, vn, vm);
615 case 0x2:
616 return new SHA256SU1(machInst, vd, vn, vm);
617 case 0x3:
618 return new Unknown(machInst);
619 default:
620 M5_UNREACHABLE;
621 }
622 } else {
624 switch (c) {
623 switch (size) {
624 case 0x0:
625 return new SHA1C(machInst, vd, vn, vm);
626 case 0x1:
627 return new SHA1P(machInst, vd, vn, vm);
628 case 0x2:
629 return new SHA1M(machInst, vd, vn, vm);
630 case 0x3:
631 return new SHA1SU0(machInst, vd, vn, vm);
632 default:
633 M5_UNREACHABLE;
634 }
635 }
636 }
637 return new Unknown(machInst);
638 case 0xd:
640 if (b) {
639 if (o1) {
640 if (u) {
642 if (bits(c, 1) == 0) {
641 if (bits(size, 1) == 0) {
642 if (q) {
643 return new NVmulQFp<float>(machInst, vd, vn, vm);
644 } else {
645 return new NVmulDFp<float>(machInst, vd, vn, vm);
646 }
647 } else {
648 return new Unknown(machInst);
649 }
650 } else {
652 if (bits(c, 1) == 0) {
651 if (bits(size, 1) == 0) {
652 if (q) {
653 return new NVmlaQFp<float>(machInst, vd, vn, vm);
654 } else {
655 return new NVmlaDFp<float>(machInst, vd, vn, vm);
656 }
657 } else {
658 if (q) {
659 return new NVmlsQFp<float>(machInst, vd, vn, vm);
660 } else {
661 return new NVmlsDFp<float>(machInst, vd, vn, vm);
662 }
663 }
664 }
665 } else {
666 if (u) {
668 if (bits(c, 1) == 0) {
667 if (bits(size, 1) == 0) {
668 if (q) {
669 return new VpaddQFp<float>(machInst, vd, vn, vm);
670 } else {
671 return new VpaddDFp<float>(machInst, vd, vn, vm);
672 }
673 } else {
674 if (q) {
675 return new VabdQFp<float>(machInst, vd, vn, vm);
676 } else {
677 return new VabdDFp<float>(machInst, vd, vn, vm);
678 }
679 }
680 } else {
682 if (bits(c, 1) == 0) {
681 if (bits(size, 1) == 0) {
682 if (q) {
683 return new VaddQFp<float>(machInst, vd, vn, vm);
684 } else {
685 return new VaddDFp<float>(machInst, vd, vn, vm);
686 }
687 } else {
688 if (q) {
689 return new VsubQFp<float>(machInst, vd, vn, vm);
690 } else {
691 return new VsubDFp<float>(machInst, vd, vn, vm);
692 }
693 }
694 }
695 }
696 case 0xe:
698 if (b) {
697 if (o1) {
698 if (u) {
700 if (bits(c, 1) == 0) {
699 if (bits(size, 1) == 0) {
700 if (q) {
701 return new VacgeQFp<float>(machInst, vd, vn, vm);
702 } else {
703 return new VacgeDFp<float>(machInst, vd, vn, vm);
704 }
705 } else {
706 if (q) {
707 return new VacgtQFp<float>(machInst, vd, vn, vm);
708 } else {
709 return new VacgtDFp<float>(machInst, vd, vn, vm);
710 }
711 }
712 } else {
713 return new Unknown(machInst);
714 }
715 } else {
716 if (u) {
718 if (bits(c, 1) == 0) {
717 if (bits(size, 1) == 0) {
718 if (q) {
719 return new VcgeQFp<float>(machInst, vd, vn, vm);
720 } else {
721 return new VcgeDFp<float>(machInst, vd, vn, vm);
722 }
723 } else {
724 if (q) {
725 return new VcgtQFp<float>(machInst, vd, vn, vm);
726 } else {
727 return new VcgtDFp<float>(machInst, vd, vn, vm);
728 }
729 }
730 } else {
732 if (bits(c, 1) == 0) {
731 if (bits(size, 1) == 0) {
732 if (q) {
733 return new VceqQFp<float>(machInst, vd, vn, vm);
734 } else {
735 return new VceqDFp<float>(machInst, vd, vn, vm);
736 }
737 } else {
738 return new Unknown(machInst);
739 }
740 }
741 }
742 case 0xf:
744 if (b) {
743 if (o1) {
744 if (u) {
745 return new Unknown(machInst);
746 } else {
748 if (bits(c, 1) == 0) {
747 if (bits(size, 1) == 0) {
748 if (q) {
749 return new VrecpsQFp<float>(machInst, vd, vn, vm);
750 } else {
751 return new VrecpsDFp<float>(machInst, vd, vn, vm);
752 }
753 } else {
754 if (q) {
755 return new VrsqrtsQFp<float>(machInst, vd, vn, vm);
756 } else {
757 return new VrsqrtsDFp<float>(machInst, vd, vn, vm);
758 }
759 }
760 }
761 } else {
762 if (u) {
764 if (bits(c, 1) == 0) {
763 if (bits(size, 1) == 0) {
764 if (q) {
765 return new VpmaxQFp<float>(machInst, vd, vn, vm);
766 } else {
767 return new VpmaxDFp<float>(machInst, vd, vn, vm);
768 }
769 } else {
770 if (q) {
771 return new VpminQFp<float>(machInst, vd, vn, vm);
772 } else {
773 return new VpminDFp<float>(machInst, vd, vn, vm);
774 }
775 }
776 } else {
778 if (bits(c, 1) == 0) {
777 if (bits(size, 1) == 0) {
778 if (q) {
779 return new VmaxQFp<float>(machInst, vd, vn, vm);
780 } else {
781 return new VmaxDFp<float>(machInst, vd, vn, vm);
782 }
783 } else {
784 if (q) {
785 return new VminQFp<float>(machInst, vd, vn, vm);

--- 111 unchanged lines hidden (view full) ---

897 }
898 }
899 return new Unknown(machInst);
900 }
901
902 static StaticInstPtr
903 decodeNeonTwoRegAndShift(ExtMachInst machInst)
904 {
906 const uint32_t a = bits(machInst, 11, 8);
905 const uint32_t opc = bits(machInst, 11, 8);
906 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
908 const bool b = bits(machInst, 6);
907 const bool q = bits(machInst, 6);
908 const bool l = bits(machInst, 7);
909 const IntRegIndex vd =
910 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
911 (bits(machInst, 22) << 4)));
912 const IntRegIndex vm =
913 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
914 (bits(machInst, 5) << 4)));
915 unsigned imm6 = bits(machInst, 21, 16);

--- 5 unchanged lines hidden (view full) ---

921 if (bitSel & imm)
922 break;
923 else if (!size)
924 return new Unknown(machInst);
925 size--;
926 }
927 lShiftAmt = imm6 & ~bitSel;
928 unsigned rShiftAmt = 0;
930 if (a != 0xe && a != 0xf) {
929 if (opc != 0xe && opc != 0xf) {
930 if (size > 2)
931 rShiftAmt = 64 - imm6;
932 else
933 rShiftAmt = 2 * (8 << size) - imm6;
934 }
935
937 switch (a) {
936 switch (opc) {
937 case 0x0:
938 return decodeNeonUSTwoShiftReg<NVshrD, NVshrQ>(
940 b, u, size, machInst, vd, vm, rShiftAmt);
939 q, u, size, machInst, vd, vm, rShiftAmt);
940 case 0x1:
941 return decodeNeonUSTwoShiftReg<NVsraD, NVsraQ>(
943 b, u, size, machInst, vd, vm, rShiftAmt);
942 q, u, size, machInst, vd, vm, rShiftAmt);
943 case 0x2:
944 return decodeNeonUSTwoShiftReg<NVrshrD, NVrshrQ>(
946 b, u, size, machInst, vd, vm, rShiftAmt);
945 q, u, size, machInst, vd, vm, rShiftAmt);
946 case 0x3:
947 return decodeNeonUSTwoShiftReg<NVrsraD, NVrsraQ>(
949 b, u, size, machInst, vd, vm, rShiftAmt);
948 q, u, size, machInst, vd, vm, rShiftAmt);
949 case 0x4:
950 if (u) {
951 return decodeNeonUTwoShiftReg<NVsriD, NVsriQ>(
953 b, size, machInst, vd, vm, rShiftAmt);
952 q, size, machInst, vd, vm, rShiftAmt);
953 } else {
954 return new Unknown(machInst);
955 }
956 case 0x5:
957 if (u) {
958 return decodeNeonUTwoShiftReg<NVsliD, NVsliQ>(
960 b, size, machInst, vd, vm, lShiftAmt);
959 q, size, machInst, vd, vm, lShiftAmt);
960 } else {
961 return decodeNeonUTwoShiftReg<NVshlD, NVshlQ>(
963 b, size, machInst, vd, vm, lShiftAmt);
962 q, size, machInst, vd, vm, lShiftAmt);
963 }
964 case 0x6:
965 case 0x7:
966 if (u) {
968 if (a == 0x6) {
967 if (opc == 0x6) {
968 return decodeNeonSTwoShiftReg<NVqshlusD, NVqshlusQ>(
970 b, size, machInst, vd, vm, lShiftAmt);
969 q, size, machInst, vd, vm, lShiftAmt);
970 } else {
971 return decodeNeonUTwoShiftReg<NVqshluD, NVqshluQ>(
973 b, size, machInst, vd, vm, lShiftAmt);
972 q, size, machInst, vd, vm, lShiftAmt);
973 }
974 } else {
975 return decodeNeonSTwoShiftReg<NVqshlD, NVqshlQ>(
977 b, size, machInst, vd, vm, lShiftAmt);
976 q, size, machInst, vd, vm, lShiftAmt);
977 }
978 case 0x8:
979 if (l) {
980 return new Unknown(machInst);
981 } else if (u) {
982 return decodeNeonSTwoShiftSReg<NVqshruns, NVqrshruns>(
984 b, size, machInst, vd, vm, rShiftAmt);
983 q, size, machInst, vd, vm, rShiftAmt);
984 } else {
985 return decodeNeonUTwoShiftSReg<NVshrn, NVrshrn>(
987 b, size, machInst, vd, vm, rShiftAmt);
986 q, size, machInst, vd, vm, rShiftAmt);
987 }
988 case 0x9:
989 if (l) {
990 return new Unknown(machInst);
991 } else if (u) {
992 return decodeNeonUTwoShiftSReg<NVqshrun, NVqrshrun>(
994 b, size, machInst, vd, vm, rShiftAmt);
993 q, size, machInst, vd, vm, rShiftAmt);
994 } else {
995 return decodeNeonSTwoShiftSReg<NVqshrn, NVqrshrn>(
997 b, size, machInst, vd, vm, rShiftAmt);
996 q, size, machInst, vd, vm, rShiftAmt);
997 }
998 case 0xa:
1000 if (l || b) {
999 if (l || q) {
1000 return new Unknown(machInst);
1001 } else {
1002 return decodeNeonUSTwoShiftSReg<NVmovl, NVshll>(
1003 lShiftAmt, u, size, machInst, vd, vm, lShiftAmt);
1004 }
1005 case 0xe:
1006 if (l) {
1007 return new Unknown(machInst);
1008 } else {
1009 if (bits(imm6, 5) == 0)
1010 return new Unknown(machInst);
1011 if (u) {
1013 if (b) {
1012 if (q) {
1013 return new NVcvtu2fpQ<float>(
1014 machInst, vd, vm, 64 - imm6);
1015 } else {
1016 return new NVcvtu2fpD<float>(
1017 machInst, vd, vm, 64 - imm6);
1018 }
1019 } else {
1021 if (b) {
1020 if (q) {
1021 return new NVcvts2fpQ<float>(
1022 machInst, vd, vm, 64 - imm6);
1023 } else {
1024 return new NVcvts2fpD<float>(
1025 machInst, vd, vm, 64 - imm6);
1026 }
1027 }
1028 }
1029 case 0xf:
1030 if (l) {
1031 return new Unknown(machInst);
1032 } else {
1033 if (bits(imm6, 5) == 0)
1034 return new Unknown(machInst);
1035 if (u) {
1037 if (b) {
1036 if (q) {
1037 return new NVcvt2ufxQ<float>(
1038 machInst, vd, vm, 64 - imm6);
1039 } else {
1040 return new NVcvt2ufxD<float>(
1041 machInst, vd, vm, 64 - imm6);
1042 }
1043 } else {
1045 if (b) {
1044 if (q) {
1045 return new NVcvt2sfxQ<float>(
1046 machInst, vd, vm, 64 - imm6);
1047 } else {
1048 return new NVcvt2sfxD<float>(
1049 machInst, vd, vm, 64 - imm6);
1050 }
1051 }
1052 }
1053 }
1054 return new Unknown(machInst);
1055 }
1056
1057 static StaticInstPtr
1058 decodeNeonThreeRegDiffLengths(ExtMachInst machInst)
1059 {
1060 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
1062 const uint32_t a = bits(machInst, 11, 8);
1061 const uint32_t opc = bits(machInst, 11, 8);
1062 const IntRegIndex vd =
1063 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
1064 (bits(machInst, 22) << 4)));
1065 const IntRegIndex vn =
1066 (IntRegIndex)(2 * (bits(machInst, 19, 16) |
1067 (bits(machInst, 7) << 4)));
1068 const IntRegIndex vm =
1069 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
1070 (bits(machInst, 5) << 4)));
1071 const unsigned size = bits(machInst, 21, 20);
1073 switch (a) {
1072 switch (opc) {
1073 case 0x0:
1074 return decodeNeonUSThreeUSReg<Vaddl>(
1075 u, size, machInst, vd, vn, vm);
1076 case 0x1:
1077 return decodeNeonUSThreeUSReg<Vaddw>(
1078 u, size, machInst, vd, vn, vm);
1079 case 0x2:
1080 return decodeNeonUSThreeUSReg<Vsubl>(

--- 64 unchanged lines hidden (view full) ---

1145 }
1146 return new Unknown(machInst);
1147 }
1148
1149 static StaticInstPtr
1150 decodeNeonTwoRegScalar(ExtMachInst machInst)
1151 {
1152 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
1154 const uint32_t a = bits(machInst, 11, 8);
1153 const uint32_t opc = bits(machInst, 11, 8);
1154 const unsigned size = bits(machInst, 21, 20);
1155 const IntRegIndex vd =
1156 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
1157 (bits(machInst, 22) << 4)));
1158 const IntRegIndex vn =
1159 (IntRegIndex)(2 * (bits(machInst, 19, 16) |
1160 (bits(machInst, 7) << 4)));
1161 const IntRegIndex vm = (size == 2) ?
1162 (IntRegIndex)(2 * bits(machInst, 3, 0)) :
1163 (IntRegIndex)(2 * bits(machInst, 2, 0));
1164 const unsigned index = (size == 2) ? (unsigned)bits(machInst, 5) :
1165 (bits(machInst, 3) | (bits(machInst, 5) << 1));
1167 switch (a) {
1166 switch (opc) {
1167 case 0x0:
1168 if (u) {
1169 switch (size) {
1170 case 1:
1171 return new VmlasQ<uint16_t>(machInst, vd, vn, vm, index);
1172 case 2:
1173 return new VmlasQ<uint32_t>(machInst, vd, vn, vm, index);
1174 default:

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1403 }
1404 }
1405 return new Unknown(machInst);
1406 }
1407
1408 static StaticInstPtr
1409 decodeNeonTwoRegMisc(ExtMachInst machInst)
1410 {
1412 const uint32_t a = bits(machInst, 17, 16);
1411 const uint32_t opc1 = bits(machInst, 17, 16);
1412 const uint32_t b = bits(machInst, 10, 6);
1413 const bool q = bits(machInst, 6);
1414 const IntRegIndex vd =
1415 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
1416 (bits(machInst, 22) << 4)));
1417 const IntRegIndex vm =
1418 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
1419 (bits(machInst, 5) << 4)));
1420 const unsigned size = bits(machInst, 19, 18);
1422 switch (a) {
1421 switch (opc1) {
1422 case 0x0:
1423 switch (bits(b, 4, 1)) {
1424 case 0x0:
1425 switch (size) {
1426 case 0:
1427 if (q) {
1428 return new NVrev64Q<uint8_t>(machInst, vd, vm);
1429 } else {

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1741 return new Unknown(machInst);
1742 }
1743
1744 StaticInstPtr
1745 decodeNeonData(ExtMachInst machInst)
1746 {
1747 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
1748 const uint32_t a = bits(machInst, 23, 19);
1750 const uint32_t b = bits(machInst, 11, 8);
1749 const uint32_t q = bits(machInst, 11, 8);
1750 const uint32_t c = bits(machInst, 7, 4);
1751 if (bits(a, 4) == 0) {
1752 return decodeNeonThreeRegistersSameLength(machInst);
1753 } else if ((c & 0x9) == 1) {
1754 if ((a & 0x7) == 0) {
1755 return decodeNeonOneRegModImm(machInst);
1756 } else {
1757 return decodeNeonTwoRegAndShift(machInst);

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1781 if (imm4 >= 16 && !q)
1782 return new Unknown(machInst);
1783 if (q) {
1784 return new NVextQ<uint8_t>(machInst, vd, vn, vm, imm4);
1785 } else {
1786 return new NVextD<uint8_t>(machInst, vd, vn, vm, imm4);
1787 }
1788 }
1790 } else if (bits(b, 3) == 0 && bits(c, 0) == 0) {
1789 } else if (bits(q, 3) == 0 && bits(c, 0) == 0) {
1790 return decodeNeonTwoRegMisc(machInst);
1792 } else if (bits(b, 3, 2) == 0x2 && bits(c, 0) == 0) {
1791 } else if (bits(q, 3, 2) == 0x2 && bits(c, 0) == 0) {
1792 unsigned length = bits(machInst, 9, 8) + 1;
1793 if ((uint32_t)vn / 2 + length > 32)
1794 return new Unknown(machInst);
1795 if (bits(machInst, 6) == 0) {
1796 switch (length) {
1797 case 1:
1798 return new NVtbl1(machInst, vd, vn, vm);
1799 case 2:

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1810 case 2:
1811 return new NVtbx2(machInst, vd, vn, vm);
1812 case 3:
1813 return new NVtbx3(machInst, vd, vn, vm);
1814 case 4:
1815 return new NVtbx4(machInst, vd, vn, vm);
1816 }
1817 }
1819 } else if (b == 0xc && (c & 0x9) == 0) {
1818 } else if (q == 0xc && (c & 0x9) == 0) {
1819 unsigned imm4 = bits(machInst, 19, 16);
1820 if (bits(imm4, 2, 0) == 0)
1821 return new Unknown(machInst);
1822 unsigned size = 0;
1823 while ((imm4 & 0x1) == 0) {
1824 size++;
1825 imm4 >>= 1;
1826 }

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2021 }
2022 }
2023 StaticInstPtr
2024 decodeShortFpTransfer(ExtMachInst machInst)
2025 {
2026 const uint32_t l = bits(machInst, 20);
2027 const uint32_t c = bits(machInst, 8);
2028 const uint32_t a = bits(machInst, 23, 21);
2030 const uint32_t b = bits(machInst, 6, 5);
2029 const uint32_t q = bits(machInst, 6, 5);
2030 const uint32_t o1 = bits(machInst, 18);
2031 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
2032 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
2033 // Determine if this is backported aarch64 FP instruction
2034 const bool b31_b24 = bits(machInst, 31, 24) == 0xFE;
2035 const bool b23 = bits(machInst, 23);
2036 const bool b21_b19 = bits(machInst, 21, 19) == 0x7;
2037 const bool b11_b9 = bits(machInst, 11, 9) == 0x5;

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2251 } else if (bits(machInst, 5) == 1) {
2252 return new VmovCoreRegH(machInst, (IntRegIndex)vd,
2253 rt, bits(machInst, 6));
2254 } else if (bits(machInst, 6) == 0) {
2255 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
2256 } else {
2257 return new Unknown(machInst);
2258 }
2260 } else if (bits(b, 1) == 0) {
2259 } else if (bits(q, 1) == 0) {
2260 bool q = bits(machInst, 21);
2261 unsigned be = (bits(machInst, 22) << 1) | (bits(machInst, 5));
2262 IntRegIndex vd = (IntRegIndex)(2 * (uint32_t)
2263 (bits(machInst, 19, 16) | (bits(machInst, 7) << 4)));
2264 IntRegIndex rt = (IntRegIndex)(uint32_t)
2265 bits(machInst, 15, 12);
2266 if (q) {
2267 switch (be) {

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