1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010-2011,2016 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 1933 unchanged lines hidden (view full) --- 1945 decodeShortFpTransfer(ExtMachInst machInst) 1946 { 1947 const uint32_t l = bits(machInst, 20); 1948 const uint32_t c = bits(machInst, 8); 1949 const uint32_t a = bits(machInst, 23, 21); 1950 const uint32_t b = bits(machInst, 6, 5); 1951 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 1952 (machInst.thumb == 0 && machInst.condCode == 0xf)) { |
1953 // Determine if this is backported aarch64 FP instruction 1954 const bool b31_b24 = bits(machInst, 31, 24) == 0xFE; 1955 const bool b23 = bits(machInst, 23); 1956 const bool b21_b18 = bits(machInst, 21, 18) == 0xE; 1957 const bool b11_b9 = bits(machInst, 11, 9) == 0x5; 1958 const bool sz = bits(machInst, 8); 1959 const bool b7_b6 = bits(machInst, 7, 6) == 0x1; 1960 const bool b6 = bits(machInst, 6) == 0x0; 1961 const bool b4 = bits(machInst, 4) == 0x0; 1962 if (b31_b24 && b23 && b21_b18 && b11_b9 && b7_b6 && b4) { 1963 // VINT* Integer Rounding Instructon 1964 const uint32_t rm = bits(machInst, 17, 16); 1965 1966 if (sz) { 1967 const IntRegIndex vd = 1968 (IntRegIndex)((bits(machInst, 22) << 5) | 1969 (bits(machInst, 15, 12) << 1)); 1970 const IntRegIndex vm = 1971 (IntRegIndex)((bits(machInst, 5) << 5) | 1972 (bits(machInst, 3, 0) << 1)); 1973 switch(rm) { 1974 case 0x0: 1975 return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm, 1976 true); 1977 case 0x1: 1978 return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm, 1979 true); 1980 case 0x2: 1981 return decodeVfpRegRegOp<VRIntPD>(machInst, vd, vm, 1982 true); 1983 case 0x3: 1984 return decodeVfpRegRegOp<VRIntMD>(machInst, vd, vm, 1985 true); 1986 default: return new Unknown(machInst); 1987 } 1988 } else { 1989 const IntRegIndex vd = 1990 (IntRegIndex)(bits(machInst, 22) | 1991 (bits(machInst, 15, 12) << 1)); 1992 const IntRegIndex vm = 1993 (IntRegIndex)(bits(machInst, 5) | 1994 (bits(machInst, 3, 0) << 1)); 1995 switch(rm) { 1996 case 0x0: 1997 return decodeVfpRegRegOp<VRIntAS>(machInst, vd, vm, 1998 false); 1999 case 0x1: 2000 return decodeVfpRegRegOp<VRIntNS>(machInst, vd, vm, 2001 false); 2002 case 0x2: 2003 return decodeVfpRegRegOp<VRIntPS>(machInst, vd, vm, 2004 false); 2005 case 0x3: 2006 return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm, 2007 false); 2008 default: return new Unknown(machInst); 2009 } 2010 } 2011 } else if (b31_b24 && !b23 && b11_b9 && b6 && b4){ 2012 // VSEL* floating point conditional select 2013 2014 ConditionCode cond; 2015 switch(bits(machInst, 21, 20)) { 2016 case 0x0: cond = COND_EQ; break; 2017 case 0x1: cond = COND_VS; break; 2018 case 0x2: cond = COND_GE; break; 2019 case 0x3: cond = COND_GT; break; 2020 } 2021 2022 if (sz) { 2023 const IntRegIndex vd = 2024 (IntRegIndex)((bits(machInst, 22) << 5) | 2025 (bits(machInst, 15, 12) << 1)); 2026 const IntRegIndex vm = 2027 (IntRegIndex)((bits(machInst, 5) << 5) | 2028 (bits(machInst, 3, 0) << 1)); 2029 const IntRegIndex vn = 2030 (IntRegIndex)((bits(machInst, 7) << 5) | 2031 (bits(machInst, 19, 16) << 1)); 2032 return new VselD(machInst, vd, vn, vm, cond); 2033 } else { 2034 const IntRegIndex vd = 2035 (IntRegIndex)(bits(machInst, 22) | 2036 (bits(machInst, 15, 12) << 1)); 2037 const IntRegIndex vm = 2038 (IntRegIndex)(bits(machInst, 5) | 2039 (bits(machInst, 3, 0) << 1)); 2040 const IntRegIndex vn = 2041 (IntRegIndex)((bits(machInst, 19, 16) << 1) | 2042 bits(machInst, 7)); 2043 return new VselS(machInst, vd, vn, vm, cond); 2044 } 2045 } else { 2046 return new Unknown(machInst); 2047 } |
2048 } 2049 if (l == 0 && c == 0) { 2050 if (a == 0) { 2051 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 2052 bits(machInst, 7); 2053 const IntRegIndex rt = 2054 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2055 if (bits(machInst, 20) == 1) { --- 597 unchanged lines hidden --- |