2036a2037
>
2047,2048c2048,2049
< StaticInstPtr
< decodeShortFpTransfer(ExtMachInst machInst)
---
>
> IntRegIndex decodeFpVn(ExtMachInst machInst, uint32_t size)
2050,2069c2051,2104
< const uint32_t l = bits(machInst, 20);
< const uint32_t c = bits(machInst, 8);
< const uint32_t a = bits(machInst, 23, 21);
< const uint32_t q = bits(machInst, 6, 5);
< const uint32_t o1 = bits(machInst, 18);
< if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
< (machInst.thumb == 0 && machInst.condCode == 0xf)) {
< // Determine if this is backported aarch64 FP instruction
< const bool b31_b24 = bits(machInst, 31, 24) == 0xFE;
< const bool b23 = bits(machInst, 23);
< const bool b21_b19 = bits(machInst, 21, 19) == 0x7;
< const bool b11_b9 = bits(machInst, 11, 9) == 0x5;
< const uint32_t size = bits(machInst, 9, 8);
< const bool op3 = bits(machInst, 6);
< const bool b4 = bits(machInst, 4) == 0x0;
< const uint32_t rm = bits(machInst, 17, 16);
< IntRegIndex vd = decodeFpVd(machInst, size, false);
< IntRegIndex vm = decodeFpVm(machInst, size, false);
< IntRegIndex vdInt = decodeFpVd(machInst, size, true);
< if (b31_b24 && b23 && b21_b19 && b11_b9 && op3 && b4) {
---
> if (size == 3) {
> return (IntRegIndex)((bits(machInst, 7) << 5) |
> (bits(machInst, 19, 16) << 1));
> } else {
> return (IntRegIndex)(bits(machInst, 7) |
> (bits(machInst, 19, 16) << 1));
> }
> }
>
> StaticInstPtr
> decodeFloatingPointDataProcessing(ExtMachInst machInst) {
> const uint32_t op0 = bits(machInst, 23, 20);
> const uint32_t op1 = bits(machInst, 19, 16);
> const uint32_t op2 = bits(machInst, 9, 8);
> const uint32_t op3 = bits(machInst, 6);
> const uint32_t rm = bits(machInst, 17, 16);
> const uint32_t size = bits(machInst, 9, 8);
> IntRegIndex vd = decodeFpVd(machInst, size, false);
> IntRegIndex vm = decodeFpVm(machInst, size, false);
> IntRegIndex vdInt = decodeFpVd(machInst, size, true);
> IntRegIndex vn = decodeFpVn(machInst, size);
> if (bits(machInst, 31, 24) == 0xFE && !bits(machInst, 4)) {
> if (bits(op0, 3) == 0 && op2 != 0 && !op3){
> ConditionCode cond;
> switch(bits(machInst, 21, 20)) {
> case 0x0: cond = COND_EQ; break;
> case 0x1: cond = COND_VS; break;
> case 0x2: cond = COND_GE; break;
> case 0x3: cond = COND_GT; break;
> }
> if (size == 3) {
> return new VselD(machInst, vd, vn, vm, cond);
> } else {
> return new VselS(machInst, vd, vn, vm, cond);
> }
> } else if (bits(op0, 3) == 1 && bits(op0, 1, 0) == 0 && op2 != 0) {
> const bool op = bits(machInst, 6);
> if (op) {
> if (size == 1) {
> return new FailUnimplemented("vminnm.f16", machInst);
> }
> return decodeNeonSizeSingleDouble<VminnmS, VminnmD>(
> size, machInst, vd, vn, vm);
> } else {
> if (size == 1) {
> return new FailUnimplemented("vmaxnm.f16", machInst);
> }
> return decodeNeonSizeSingleDouble<VmaxnmS, VmaxnmD>(
> size, machInst, vd, vn, vm);
> }
> } else if (bits(op0, 3) && bits(op0, 1, 0) == 3 &&
> bits(op1, 3) && op2 != 0 && op3)
> {
> const uint32_t o1 = bits(machInst, 18);
2071d2105
< // VINT* Integer Rounding Instruction
2108c2142
< case 0x0:
---
> case 0x0:
2110c2144
< case 0x0:
---
> case 0x0:
2112c2146
< case 0x1:
---
> case 0x1:
2115c2149
< case 0x2:
---
> case 0x2:
2121c2155
< case 0x3:
---
> case 0x3:
2127c2161
< default: return new Unknown(machInst);
---
> default: return new Unknown(machInst);
2129c2163
< case 0x1:
---
> case 0x1:
2131c2165
< case 0x0:
---
> case 0x0:
2133c2167
< case 0x1:
---
> case 0x1:
2136c2170
< case 0x2:
---
> case 0x2:
2142c2176
< case 0x3:
---
> case 0x3:
2148c2182
< default: return new Unknown(machInst);
---
> default: return new Unknown(machInst);
2150c2184
< case 0x2:
---
> case 0x2:
2152c2186
< case 0x0:
---
> case 0x0:
2154c2188
< case 0x1:
---
> case 0x1:
2157c2191
< case 0x2:
---
> case 0x2:
2163c2197
< case 0x3:
---
> case 0x3:
2169c2203
< default: return new Unknown(machInst);
---
> default: return new Unknown(machInst);
2171c2205
< case 0x3:
---
> case 0x3:
2173c2207
< case 0x0:
---
> case 0x0:
2175c2209
< case 0x1:
---
> case 0x1:
2178c2212
< case 0x2:
---
> case 0x2:
2184c2218
< case 0x3:
---
> case 0x3:
2190c2224
< default: return new Unknown(machInst);
---
> default: return new Unknown(machInst);
2192c2226
< default: return new Unknown(machInst);
---
> default: return new Unknown(machInst);
2195,2216d2228
< } else if (b31_b24 && !b23 && b11_b9 && !op3 && b4){
< // VSEL* floating point conditional select
<
< ConditionCode cond;
< switch(bits(machInst, 21, 20)) {
< case 0x0: cond = COND_EQ; break;
< case 0x1: cond = COND_VS; break;
< case 0x2: cond = COND_GE; break;
< case 0x3: cond = COND_GT; break;
< }
<
< if (size == 3) {
< const IntRegIndex vn =
< (IntRegIndex)((bits(machInst, 7) << 5) |
< (bits(machInst, 19, 16) << 1));
< return new VselD(machInst, vd, vn, vm, cond);
< } else {
< const IntRegIndex vn =
< (IntRegIndex)((bits(machInst, 19, 16) << 1) |
< bits(machInst, 7));
< return new VselS(machInst, vd, vn, vm, cond);
< }
2219a2232,2233
> } else {
> return new Unknown(machInst);
2220a2235,2247
> }
>
> StaticInstPtr
> decodeShortFpTransfer(ExtMachInst machInst)
> {
> if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
> (machInst.thumb == 0 && machInst.condCode == 0xf)) {
> return decodeFloatingPointDataProcessing(machInst);
> }
> const uint32_t l = bits(machInst, 20);
> const uint32_t c = bits(machInst, 8);
> const uint32_t a = bits(machInst, 23, 21);
> const uint32_t q = bits(machInst, 6, 5);