3c3
< // Copyright (c) 2010-2011, 2016-2018 ARM Limited
---
> // Copyright (c) 2010-2011, 2016-2019 ARM Limited
2003a2004,2023
> IntRegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt)
> {
> if (!isInt and size == 3) {
> return (IntRegIndex)((bits(machInst, 22) << 5) |
> (bits(machInst, 15, 12) << 1));
> } else {
> return (IntRegIndex)(bits(machInst, 22) |
> (bits(machInst, 15, 12) << 1));
> }
> }
> IntRegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt)
> {
> if (!isInt and size == 3) {
> return (IntRegIndex)((bits(machInst, 5) << 5) |
> (bits(machInst, 3, 0) << 1));
> } else {
> return (IntRegIndex)(bits(machInst, 5) |
> (bits(machInst, 3, 0) << 1));
> }
> }
2010a2031
> const uint32_t o1 = bits(machInst, 18);
2016c2037
< const bool b21_b18 = bits(machInst, 21, 18) == 0xE;
---
> const bool b21_b19 = bits(machInst, 21, 19) == 0x7;
2018,2020c2039,2040
< const bool sz = bits(machInst, 8);
< const bool b7_b6 = bits(machInst, 7, 6) == 0x1;
< const bool b6 = bits(machInst, 6) == 0x0;
---
> const uint32_t size = bits(machInst, 9, 8);
> const bool op3 = bits(machInst, 6);
2022,2071c2042,2167
< if (b31_b24 && b23 && b21_b18 && b11_b9 && b7_b6 && b4) {
< // VINT* Integer Rounding Instructon
< const uint32_t rm = bits(machInst, 17, 16);
<
< if (sz) {
< const IntRegIndex vd =
< (IntRegIndex)((bits(machInst, 22) << 5) |
< (bits(machInst, 15, 12) << 1));
< const IntRegIndex vm =
< (IntRegIndex)((bits(machInst, 5) << 5) |
< (bits(machInst, 3, 0) << 1));
< switch(rm) {
< case 0x0:
< return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm,
< true);
< case 0x1:
< return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm,
< true);
< case 0x2:
< return decodeVfpRegRegOp<VRIntPD>(machInst, vd, vm,
< true);
< case 0x3:
< return decodeVfpRegRegOp<VRIntMD>(machInst, vd, vm,
< true);
< default: return new Unknown(machInst);
< }
< } else {
< const IntRegIndex vd =
< (IntRegIndex)(bits(machInst, 22) |
< (bits(machInst, 15, 12) << 1));
< const IntRegIndex vm =
< (IntRegIndex)(bits(machInst, 5) |
< (bits(machInst, 3, 0) << 1));
< switch(rm) {
< case 0x0:
< return decodeVfpRegRegOp<VRIntAS>(machInst, vd, vm,
< false);
< case 0x1:
< return decodeVfpRegRegOp<VRIntNS>(machInst, vd, vm,
< false);
< case 0x2:
< return decodeVfpRegRegOp<VRIntPS>(machInst, vd, vm,
< false);
< case 0x3:
< return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm,
< false);
< default: return new Unknown(machInst);
< }
< }
< } else if (b31_b24 && !b23 && b11_b9 && b6 && b4){
---
> const uint32_t rm = bits(machInst, 17, 16);
> IntRegIndex vd = decodeFpVd(machInst, size, false);
> IntRegIndex vm = decodeFpVm(machInst, size, false);
> IntRegIndex vdInt = decodeFpVd(machInst, size, true);
> if (b31_b24 && b23 && b21_b19 && b11_b9 && op3 && b4) {
> if (o1 == 0) {
> // VINT* Integer Rounding Instruction
> if (size == 3) {
> switch(rm) {
> case 0x0:
> return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm,
> true);
> case 0x1:
> return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm,
> true);
> case 0x2:
> return decodeVfpRegRegOp<VRIntPD>(machInst, vd, vm,
> true);
> case 0x3:
> return decodeVfpRegRegOp<VRIntMD>(machInst, vd, vm,
> true);
> default: return new Unknown(machInst);
> }
> } else {
> switch(rm) {
> case 0x0:
> return decodeVfpRegRegOp<VRIntAS>(machInst, vd, vm,
> false);
> case 0x1:
> return decodeVfpRegRegOp<VRIntNS>(machInst, vd, vm,
> false);
> case 0x2:
> return decodeVfpRegRegOp<VRIntPS>(machInst, vd, vm,
> false);
> case 0x3:
> return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm,
> false);
> default: return new Unknown(machInst);
> }
> }
> } else {
> const bool op = bits(machInst, 7);
> switch(rm) {
> case 0x0:
> switch(size) {
> case 0x0:
> return new Unknown(machInst);
> case 0x1:
> return new FailUnimplemented(
> "vcvta.u32.f16", machInst);
> case 0x2:
> if (op) {
> return new VcvtaFpSIntS(machInst, vdInt, vm);
> } else {
> return new VcvtaFpUIntS(machInst, vdInt, vm);
> }
> case 0x3:
> if (op) {
> return new VcvtaFpSIntD(machInst, vdInt, vm);
> } else {
> return new VcvtaFpUIntD(machInst, vdInt, vm);
> }
> }
> case 0x1:
> switch(size) {
> case 0x0:
> return new Unknown(machInst);
> case 0x1:
> return new FailUnimplemented(
> "vcvtn.u32.f16", machInst);
> case 0x2:
> if (op) {
> return new VcvtnFpSIntS(machInst, vdInt, vm);
> } else {
> return new VcvtnFpUIntS(machInst, vdInt, vm);
> }
> case 0x3:
> if (op) {
> return new VcvtnFpSIntD(machInst, vdInt, vm);
> } else {
> return new VcvtnFpUIntD(machInst, vdInt, vm);
> }
> }
> case 0x2:
> switch(size) {
> case 0x0:
> return new Unknown(machInst);
> case 0x1:
> return new FailUnimplemented(
> "vcvtp.u32.f16", machInst);
> case 0x2:
> if (op) {
> return new VcvtpFpSIntS(machInst, vdInt, vm);
> } else {
> return new VcvtpFpUIntS(machInst, vdInt, vm);
> }
> case 0x3:
> if (op) {
> return new VcvtpFpSIntD(machInst, vdInt, vm);
> } else {
> return new VcvtpFpUIntD(machInst, vdInt, vm);
> }
> }
> case 0x3:
> switch(size) {
> case 0x0:
> return new Unknown(machInst);
> case 0x1:
> return new FailUnimplemented(
> "vcvtm.u32.f16", machInst);
> case 0x2:
> if (op) {
> return new VcvtmFpSIntS(machInst, vdInt, vm);
> } else {
> return new VcvtmFpUIntS(machInst, vdInt, vm);
> }
> case 0x3:
> if (op) {
> return new VcvtmFpSIntD(machInst, vdInt, vm);
> } else {
> return new VcvtmFpUIntD(machInst, vdInt, vm);
> }
> }
> }
> }
> } else if (b31_b24 && !b23 && b11_b9 && !op3 && b4){
2082,2088c2178
< if (sz) {
< const IntRegIndex vd =
< (IntRegIndex)((bits(machInst, 22) << 5) |
< (bits(machInst, 15, 12) << 1));
< const IntRegIndex vm =
< (IntRegIndex)((bits(machInst, 5) << 5) |
< (bits(machInst, 3, 0) << 1));
---
> if (size == 3) {
2094,2099d2183
< const IntRegIndex vd =
< (IntRegIndex)(bits(machInst, 22) |
< (bits(machInst, 15, 12) << 1));
< const IntRegIndex vm =
< (IntRegIndex)(bits(machInst, 5) |
< (bits(machInst, 3, 0) << 1));