113 } 114 case 0x2: 115 if (bits(opcode, 1, 0) == 0x2) { 116 // If rn == sp, then this is called vpush. 117 return new VLdmStm(machInst, rn, vd, single, 118 false, true, false, offset); 119 } else if (bits(opcode, 1, 0) == 0x3) { 120 return new VLdmStm(machInst, rn, vd, single, 121 false, true, true, offset); 122 } 123 // Fall through on purpose 124 case 0x3: 125 const bool up = (bits(machInst, 23) == 1); 126 const uint32_t imm = bits(machInst, 7, 0) << 2; 127 RegIndex vd; 128 if (single) { 129 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 130 (bits(machInst, 22))); 131 } else { 132 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 133 (bits(machInst, 22) << 5)); 134 } 135 if (bits(opcode, 1, 0) == 0x0) { 136 if (single) { 137 if (up) { 138 return new %(vstr_us)s(machInst, vd, rn, up, imm); 139 } else { 140 return new %(vstr_s)s(machInst, vd, rn, up, imm); 141 } 142 } else { 143 if (up) { 144 return new %(vstr_ud)s(machInst, vd, vd + 1, 145 rn, up, imm); 146 } else { 147 return new %(vstr_d)s(machInst, vd, vd + 1, 148 rn, up, imm); 149 } 150 } 151 } else if (bits(opcode, 1, 0) == 0x1) { 152 if (single) { 153 if (up) { 154 return new %(vldr_us)s(machInst, vd, rn, up, imm); 155 } else { 156 return new %(vldr_s)s(machInst, vd, rn, up, imm); 157 } 158 } else { 159 if (up) { 160 return new %(vldr_ud)s(machInst, vd, vd + 1, 161 rn, up, imm); 162 } else { 163 return new %(vldr_d)s(machInst, vd, vd + 1, 164 rn, up, imm); 165 } 166 } 167 } 168 } 169 return new Unknown(machInst); 170 } 171 ''' % { 172 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 173 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 174 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 175 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 176 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 177 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 178 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 179 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 180 } 181}}; 182 183def format ExtensionRegLoadStore() {{ 184 decode_block = ''' 185 return decodeExtensionRegLoadStore(machInst); 186 ''' 187}}; 188 189let {{ 190 header_output = ''' 191 StaticInstPtr 192 decodeShortFpTransfer(ExtMachInst machInst); 193 ''' 194 decoder_output = ''' 195 StaticInstPtr 196 decodeShortFpTransfer(ExtMachInst machInst) 197 { 198 const uint32_t l = bits(machInst, 20); 199 const uint32_t c = bits(machInst, 8); 200 const uint32_t a = bits(machInst, 23, 21); 201 const uint32_t b = bits(machInst, 6, 5); 202 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 203 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 204 return new Unknown(machInst); 205 } 206 if (l == 0 && c == 0) { 207 if (a == 0) { 208 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 209 bits(machInst, 7); 210 const IntRegIndex rt = 211 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 212 if (bits(machInst, 20) == 1) { 213 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 214 } else { 215 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 216 } 217 } else if (a == 0x7) { 218 const IntRegIndex rt = 219 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 220 uint32_t specReg = bits(machInst, 19, 16); 221 switch (specReg) { 222 case 0: 223 specReg = MISCREG_FPSID; 224 break; 225 case 1: 226 specReg = MISCREG_FPSCR; 227 break; 228 case 6: 229 specReg = MISCREG_MVFR1; 230 break; 231 case 7: 232 specReg = MISCREG_MVFR0; 233 break; 234 case 8: 235 specReg = MISCREG_FPEXC; 236 break; 237 default: 238 return new Unknown(machInst); 239 } 240 return new Vmsr(machInst, (IntRegIndex)specReg, rt); 241 } 242 } else if (l == 0 && c == 1) { 243 if (bits(a, 2) == 0) { 244 uint32_t vd = (bits(machInst, 7) << 5) | 245 (bits(machInst, 19, 16) << 1); 246 uint32_t index, size; 247 const IntRegIndex rt = 248 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 249 if (bits(machInst, 22) == 1) { 250 size = 8; 251 index = (bits(machInst, 21) << 2) | 252 bits(machInst, 6, 5); 253 } else if (bits(machInst, 5) == 1) { 254 size = 16; 255 index = (bits(machInst, 21) << 1) | 256 bits(machInst, 6); 257 } else if (bits(machInst, 6) == 0) { 258 size = 32; 259 index = bits(machInst, 21); 260 } else { 261 return new Unknown(machInst); 262 } 263 if (index >= (32 / size)) { 264 index -= (32 / size); 265 vd++; 266 } 267 switch (size) { 268 case 8: 269 return new VmovCoreRegB(machInst, (IntRegIndex)vd, 270 rt, index); 271 case 16: 272 return new VmovCoreRegH(machInst, (IntRegIndex)vd, 273 rt, index); 274 case 32: 275 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 276 } 277 } else if (bits(b, 1) == 0) { 278 // A8-594 279 return new WarnUnimplemented("vdup", machInst); 280 } 281 } else if (l == 1 && c == 0) { 282 if (a == 0) { 283 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 284 bits(machInst, 7); 285 const IntRegIndex rt = 286 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 287 if (bits(machInst, 20) == 1) { 288 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 289 } else { 290 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 291 } 292 } else if (a == 7) { 293 const IntRegIndex rt = 294 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 295 uint32_t specReg = bits(machInst, 19, 16); 296 switch (specReg) { 297 case 0: 298 specReg = MISCREG_FPSID; 299 break; 300 case 1: 301 specReg = MISCREG_FPSCR; 302 break; 303 case 6: 304 specReg = MISCREG_MVFR1; 305 break; 306 case 7: 307 specReg = MISCREG_MVFR0; 308 break; 309 case 8: 310 specReg = MISCREG_FPEXC; 311 break; 312 default: 313 return new Unknown(machInst); 314 } 315 if (rt == 0xf) { 316 CPSR cpsrMask = 0; 317 cpsrMask.n = 1; 318 cpsrMask.z = 1; 319 cpsrMask.c = 1; 320 cpsrMask.v = 1; 321 return new VmrsApsr(machInst, INTREG_CONDCODES, 322 (IntRegIndex)specReg, (uint32_t)cpsrMask); 323 } else { 324 return new Vmrs(machInst, rt, (IntRegIndex)specReg); 325 } 326 } 327 } else { 328 uint32_t vd = (bits(machInst, 7) << 5) | 329 (bits(machInst, 19, 16) << 1); 330 uint32_t index, size; 331 const IntRegIndex rt = 332 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 333 const bool u = (bits(machInst, 23) == 1); 334 if (bits(machInst, 22) == 1) { 335 size = 8; 336 index = (bits(machInst, 21) << 2) | 337 bits(machInst, 6, 5); 338 } else if (bits(machInst, 5) == 1) { 339 size = 16; 340 index = (bits(machInst, 21) << 1) | 341 bits(machInst, 6); 342 } else if (bits(machInst, 6) == 0 && !u) { 343 size = 32; 344 index = bits(machInst, 21); 345 } else { 346 return new Unknown(machInst); 347 } 348 if (index >= (32 / size)) { 349 index -= (32 / size); 350 vd++; 351 } 352 switch (size) { 353 case 8: 354 if (u) { 355 return new VmovRegCoreUB(machInst, rt, 356 (IntRegIndex)vd, index); 357 } else { 358 return new VmovRegCoreSB(machInst, rt, 359 (IntRegIndex)vd, index); 360 } 361 case 16: 362 if (u) { 363 return new VmovRegCoreUH(machInst, rt, 364 (IntRegIndex)vd, index); 365 } else { 366 return new VmovRegCoreSH(machInst, rt, 367 (IntRegIndex)vd, index); 368 } 369 case 32: 370 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 371 } 372 } 373 return new Unknown(machInst); 374 } 375 ''' 376}}; 377 378def format ShortFpTransfer() {{ 379 decode_block = ''' 380 return decodeShortFpTransfer(machInst); 381 ''' 382}}; 383 384let {{ 385 header_output = ''' 386 StaticInstPtr 387 decodeVfpData(ExtMachInst machInst); 388 ''' 389 decoder_output = ''' 390 StaticInstPtr 391 decodeVfpData(ExtMachInst machInst) 392 { 393 const uint32_t opc1 = bits(machInst, 23, 20); 394 const uint32_t opc2 = bits(machInst, 19, 16); 395 const uint32_t opc3 = bits(machInst, 7, 6); 396 //const uint32_t opc4 = bits(machInst, 3, 0); 397 const bool single = (bits(machInst, 8) == 0); 398 // Used to select between vcmp and vcmpe. 399 const bool e = (bits(machInst, 7) == 1); 400 IntRegIndex vd; 401 IntRegIndex vm; 402 IntRegIndex vn; 403 if (single) { 404 vd = (IntRegIndex)(bits(machInst, 22) | 405 (bits(machInst, 15, 12) << 1)); 406 vm = (IntRegIndex)(bits(machInst, 5) | 407 (bits(machInst, 3, 0) << 1)); 408 vn = (IntRegIndex)(bits(machInst, 7) | 409 (bits(machInst, 19, 16) << 1)); 410 } else { 411 vd = (IntRegIndex)((bits(machInst, 22) << 5) | 412 (bits(machInst, 15, 12) << 1)); 413 vm = (IntRegIndex)((bits(machInst, 5) << 5) | 414 (bits(machInst, 3, 0) << 1)); 415 vn = (IntRegIndex)((bits(machInst, 7) << 5) | 416 (bits(machInst, 19, 16) << 1)); 417 } 418 switch (opc1 & 0xb /* 1011 */) { 419 case 0x0: 420 if (bits(machInst, 6) == 0) { 421 if (single) { 422 return decodeVfpRegRegRegOp<VmlaS>( 423 machInst, vd, vn, vm, false); 424 } else { 425 return decodeVfpRegRegRegOp<VmlaD>( 426 machInst, vd, vn, vm, true); 427 } 428 } else { 429 if (single) { 430 return decodeVfpRegRegRegOp<VmlsS>( 431 machInst, vd, vn, vm, false); 432 } else { 433 return decodeVfpRegRegRegOp<VmlsD>( 434 machInst, vd, vn, vm, true); 435 } 436 } 437 case 0x1: 438 if (bits(machInst, 6) == 1) { 439 if (single) { 440 return decodeVfpRegRegRegOp<VnmlaS>( 441 machInst, vd, vn, vm, false); 442 } else { 443 return decodeVfpRegRegRegOp<VnmlaD>( 444 machInst, vd, vn, vm, true); 445 } 446 } else { 447 if (single) { 448 return decodeVfpRegRegRegOp<VnmlsS>( 449 machInst, vd, vn, vm, false); 450 } else { 451 return decodeVfpRegRegRegOp<VnmlsD>( 452 machInst, vd, vn, vm, true); 453 } 454 } 455 case 0x2: 456 if ((opc3 & 0x1) == 0) { 457 if (single) { 458 return decodeVfpRegRegRegOp<VmulS>( 459 machInst, vd, vn, vm, false); 460 } else { 461 return decodeVfpRegRegRegOp<VmulD>( 462 machInst, vd, vn, vm, true); 463 } 464 } else { 465 if (single) { 466 return decodeVfpRegRegRegOp<VnmulS>( 467 machInst, vd, vn, vm, false); 468 } else { 469 return decodeVfpRegRegRegOp<VnmulD>( 470 machInst, vd, vn, vm, true); 471 } 472 } 473 case 0x3: 474 if ((opc3 & 0x1) == 0) { 475 if (single) { 476 return decodeVfpRegRegRegOp<VaddS>( 477 machInst, vd, vn, vm, false); 478 } else { 479 return decodeVfpRegRegRegOp<VaddD>( 480 machInst, vd, vn, vm, true); 481 } 482 } else { 483 if (single) { 484 return decodeVfpRegRegRegOp<VsubS>( 485 machInst, vd, vn, vm, false); 486 } else { 487 return decodeVfpRegRegRegOp<VsubD>( 488 machInst, vd, vn, vm, true); 489 } 490 } 491 case 0x8: 492 if ((opc3 & 0x1) == 0) { 493 if (single) { 494 return decodeVfpRegRegRegOp<VdivS>( 495 machInst, vd, vn, vm, false); 496 } else { 497 return decodeVfpRegRegRegOp<VdivD>( 498 machInst, vd, vn, vm, true); 499 } 500 } 501 break; 502 case 0xb: 503 if ((opc3 & 0x1) == 0) { 504 const uint32_t baseImm = 505 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 506 if (single) { 507 uint32_t imm = vfp_modified_imm(baseImm, false); 508 return decodeVfpRegImmOp<VmovImmS>( 509 machInst, vd, imm, false); 510 } else { 511 uint64_t imm = vfp_modified_imm(baseImm, true); 512 return decodeVfpRegImmOp<VmovImmD>( 513 machInst, vd, imm, true); 514 } 515 } 516 switch (opc2) { 517 case 0x0: 518 if (opc3 == 1) { 519 if (single) { 520 return decodeVfpRegRegOp<VmovRegS>( 521 machInst, vd, vm, false); 522 } else { 523 return decodeVfpRegRegOp<VmovRegD>( 524 machInst, vd, vm, true); 525 } 526 } else { 527 if (single) { 528 return decodeVfpRegRegOp<VabsS>( 529 machInst, vd, vm, false); 530 } else { 531 return decodeVfpRegRegOp<VabsD>( 532 machInst, vd, vm, true); 533 } 534 } 535 case 0x1: 536 if (opc3 == 1) { 537 if (single) { 538 return decodeVfpRegRegOp<VnegS>( 539 machInst, vd, vm, false); 540 } else { 541 return decodeVfpRegRegOp<VnegD>( 542 machInst, vd, vm, true); 543 } 544 } else { 545 if (single) { 546 return decodeVfpRegRegOp<VsqrtS>( 547 machInst, vd, vm, false); 548 } else { 549 return decodeVfpRegRegOp<VsqrtD>( 550 machInst, vd, vm, true); 551 } 552 } 553 case 0x2: 554 case 0x3: 555 { 556 const bool toHalf = bits(machInst, 16); 557 const bool top = bits(machInst, 7); 558 if (top) { 559 if (toHalf) { 560 return new VcvtFpSFpHT(machInst, vd, vm); 561 } else { 562 return new VcvtFpHTFpS(machInst, vd, vm); 563 } 564 } else { 565 if (toHalf) { 566 return new VcvtFpSFpHB(machInst, vd, vm); 567 } else { 568 return new VcvtFpHBFpS(machInst, vd, vm); 569 } 570 } 571 } 572 case 0x4: 573 if (single) { 574 if (e) { 575 return new VcmpeS(machInst, vd, vm); 576 } else { 577 return new VcmpS(machInst, vd, vm); 578 } 579 } else { 580 if (e) { 581 return new VcmpeD(machInst, vd, vm); 582 } else { 583 return new VcmpD(machInst, vd, vm); 584 } 585 } 586 case 0x5: 587 if (single) { 588 if (e) { 589 return new VcmpeZeroS(machInst, vd, 0); 590 } else { 591 return new VcmpZeroS(machInst, vd, 0); 592 } 593 } else { 594 if (e) { 595 return new VcmpeZeroD(machInst, vd, 0); 596 } else { 597 return new VcmpZeroD(machInst, vd, 0); 598 } 599 } 600 case 0x7: 601 if (opc3 == 0x3) { 602 if (single) { 603 vm = (IntRegIndex)(bits(machInst, 5) | 604 (bits(machInst, 3, 0) << 1)); 605 return new VcvtFpSFpD(machInst, vd, vm); 606 } else { 607 vd = (IntRegIndex)(bits(machInst, 22) | 608 (bits(machInst, 15, 12) << 1)); 609 return new VcvtFpDFpS(machInst, vd, vm); 610 } 611 } 612 break; 613 case 0x8: 614 if (bits(machInst, 7) == 0) { 615 if (single) { 616 return new VcvtUIntFpS(machInst, vd, vm); 617 } else { 618 vm = (IntRegIndex)(bits(machInst, 5) | 619 (bits(machInst, 3, 0) << 1)); 620 return new VcvtUIntFpD(machInst, vd, vm); 621 } 622 } else { 623 if (single) { 624 return new VcvtSIntFpS(machInst, vd, vm); 625 } else { 626 vm = (IntRegIndex)(bits(machInst, 5) | 627 (bits(machInst, 3, 0) << 1)); 628 return new VcvtSIntFpD(machInst, vd, vm); 629 } 630 } 631 case 0xa: 632 { 633 const bool half = (bits(machInst, 7) == 0); 634 const uint32_t imm = bits(machInst, 5) | 635 (bits(machInst, 3, 0) << 1); 636 const uint32_t size = 637 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 638 if (single) { 639 if (half) { 640 return new VcvtSHFixedFpS(machInst, vd, vd, size); 641 } else { 642 return new VcvtSFixedFpS(machInst, vd, vd, size); 643 } 644 } else { 645 if (half) { 646 return new VcvtSHFixedFpD(machInst, vd, vd, size); 647 } else { 648 return new VcvtSFixedFpD(machInst, vd, vd, size); 649 } 650 } 651 } 652 case 0xb: 653 { 654 const bool half = (bits(machInst, 7) == 0); 655 const uint32_t imm = bits(machInst, 5) | 656 (bits(machInst, 3, 0) << 1); 657 const uint32_t size = 658 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 659 if (single) { 660 if (half) { 661 return new VcvtUHFixedFpS(machInst, vd, vd, size); 662 } else { 663 return new VcvtUFixedFpS(machInst, vd, vd, size); 664 } 665 } else { 666 if (half) { 667 return new VcvtUHFixedFpD(machInst, vd, vd, size); 668 } else { 669 return new VcvtUFixedFpD(machInst, vd, vd, size); 670 } 671 } 672 } 673 case 0xc: 674 if (bits(machInst, 7) == 0) { 675 if (single) { 676 return new VcvtFpUIntSR(machInst, vd, vm); 677 } else { 678 vd = (IntRegIndex)(bits(machInst, 22) | 679 (bits(machInst, 15, 12) << 1)); 680 return new VcvtFpUIntDR(machInst, vd, vm); 681 } 682 } else { 683 if (single) { 684 return new VcvtFpUIntS(machInst, vd, vm); 685 } else { 686 vd = (IntRegIndex)(bits(machInst, 22) | 687 (bits(machInst, 15, 12) << 1)); 688 return new VcvtFpUIntD(machInst, vd, vm); 689 } 690 } 691 case 0xd: 692 if (bits(machInst, 7) == 0) { 693 if (single) { 694 return new VcvtFpSIntSR(machInst, vd, vm); 695 } else { 696 vd = (IntRegIndex)(bits(machInst, 22) | 697 (bits(machInst, 15, 12) << 1)); 698 return new VcvtFpSIntDR(machInst, vd, vm); 699 } 700 } else { 701 if (single) { 702 return new VcvtFpSIntS(machInst, vd, vm); 703 } else { 704 vd = (IntRegIndex)(bits(machInst, 22) | 705 (bits(machInst, 15, 12) << 1)); 706 return new VcvtFpSIntD(machInst, vd, vm); 707 } 708 } 709 case 0xe: 710 { 711 const bool half = (bits(machInst, 7) == 0); 712 const uint32_t imm = bits(machInst, 5) | 713 (bits(machInst, 3, 0) << 1); 714 const uint32_t size = 715 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 716 if (single) { 717 if (half) { 718 return new VcvtFpSHFixedS(machInst, vd, vd, size); 719 } else { 720 return new VcvtFpSFixedS(machInst, vd, vd, size); 721 } 722 } else { 723 if (half) { 724 return new VcvtFpSHFixedD(machInst, vd, vd, size); 725 } else { 726 return new VcvtFpSFixedD(machInst, vd, vd, size); 727 } 728 } 729 } 730 case 0xf: 731 { 732 const bool half = (bits(machInst, 7) == 0); 733 const uint32_t imm = bits(machInst, 5) | 734 (bits(machInst, 3, 0) << 1); 735 const uint32_t size = 736 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 737 if (single) { 738 if (half) { 739 return new VcvtFpUHFixedS(machInst, vd, vd, size); 740 } else { 741 return new VcvtFpUFixedS(machInst, vd, vd, size); 742 } 743 } else { 744 if (half) { 745 return new VcvtFpUHFixedD(machInst, vd, vd, size); 746 } else { 747 return new VcvtFpUFixedD(machInst, vd, vd, size); 748 } 749 } 750 } 751 } 752 break; 753 } 754 return new Unknown(machInst); 755 } 756 ''' 757}}; 758 759def format VfpData() {{ 760 decode_block = ''' 761 return decodeVfpData(machInst); 762 ''' 763}};
| 118 } 119 case 0x2: 120 if (bits(opcode, 1, 0) == 0x2) { 121 // If rn == sp, then this is called vpush. 122 return new VLdmStm(machInst, rn, vd, single, 123 false, true, false, offset); 124 } else if (bits(opcode, 1, 0) == 0x3) { 125 return new VLdmStm(machInst, rn, vd, single, 126 false, true, true, offset); 127 } 128 // Fall through on purpose 129 case 0x3: 130 const bool up = (bits(machInst, 23) == 1); 131 const uint32_t imm = bits(machInst, 7, 0) << 2; 132 RegIndex vd; 133 if (single) { 134 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 135 (bits(machInst, 22))); 136 } else { 137 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 138 (bits(machInst, 22) << 5)); 139 } 140 if (bits(opcode, 1, 0) == 0x0) { 141 if (single) { 142 if (up) { 143 return new %(vstr_us)s(machInst, vd, rn, up, imm); 144 } else { 145 return new %(vstr_s)s(machInst, vd, rn, up, imm); 146 } 147 } else { 148 if (up) { 149 return new %(vstr_ud)s(machInst, vd, vd + 1, 150 rn, up, imm); 151 } else { 152 return new %(vstr_d)s(machInst, vd, vd + 1, 153 rn, up, imm); 154 } 155 } 156 } else if (bits(opcode, 1, 0) == 0x1) { 157 if (single) { 158 if (up) { 159 return new %(vldr_us)s(machInst, vd, rn, up, imm); 160 } else { 161 return new %(vldr_s)s(machInst, vd, rn, up, imm); 162 } 163 } else { 164 if (up) { 165 return new %(vldr_ud)s(machInst, vd, vd + 1, 166 rn, up, imm); 167 } else { 168 return new %(vldr_d)s(machInst, vd, vd + 1, 169 rn, up, imm); 170 } 171 } 172 } 173 } 174 return new Unknown(machInst); 175 } 176 ''' % { 177 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 178 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 179 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 180 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 181 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 182 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 183 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 184 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 185 } 186}}; 187 188def format ExtensionRegLoadStore() {{ 189 decode_block = ''' 190 return decodeExtensionRegLoadStore(machInst); 191 ''' 192}}; 193 194let {{ 195 header_output = ''' 196 StaticInstPtr 197 decodeShortFpTransfer(ExtMachInst machInst); 198 ''' 199 decoder_output = ''' 200 StaticInstPtr 201 decodeShortFpTransfer(ExtMachInst machInst) 202 { 203 const uint32_t l = bits(machInst, 20); 204 const uint32_t c = bits(machInst, 8); 205 const uint32_t a = bits(machInst, 23, 21); 206 const uint32_t b = bits(machInst, 6, 5); 207 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 208 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 209 return new Unknown(machInst); 210 } 211 if (l == 0 && c == 0) { 212 if (a == 0) { 213 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 214 bits(machInst, 7); 215 const IntRegIndex rt = 216 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 217 if (bits(machInst, 20) == 1) { 218 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 219 } else { 220 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 221 } 222 } else if (a == 0x7) { 223 const IntRegIndex rt = 224 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 225 uint32_t specReg = bits(machInst, 19, 16); 226 switch (specReg) { 227 case 0: 228 specReg = MISCREG_FPSID; 229 break; 230 case 1: 231 specReg = MISCREG_FPSCR; 232 break; 233 case 6: 234 specReg = MISCREG_MVFR1; 235 break; 236 case 7: 237 specReg = MISCREG_MVFR0; 238 break; 239 case 8: 240 specReg = MISCREG_FPEXC; 241 break; 242 default: 243 return new Unknown(machInst); 244 } 245 return new Vmsr(machInst, (IntRegIndex)specReg, rt); 246 } 247 } else if (l == 0 && c == 1) { 248 if (bits(a, 2) == 0) { 249 uint32_t vd = (bits(machInst, 7) << 5) | 250 (bits(machInst, 19, 16) << 1); 251 uint32_t index, size; 252 const IntRegIndex rt = 253 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 254 if (bits(machInst, 22) == 1) { 255 size = 8; 256 index = (bits(machInst, 21) << 2) | 257 bits(machInst, 6, 5); 258 } else if (bits(machInst, 5) == 1) { 259 size = 16; 260 index = (bits(machInst, 21) << 1) | 261 bits(machInst, 6); 262 } else if (bits(machInst, 6) == 0) { 263 size = 32; 264 index = bits(machInst, 21); 265 } else { 266 return new Unknown(machInst); 267 } 268 if (index >= (32 / size)) { 269 index -= (32 / size); 270 vd++; 271 } 272 switch (size) { 273 case 8: 274 return new VmovCoreRegB(machInst, (IntRegIndex)vd, 275 rt, index); 276 case 16: 277 return new VmovCoreRegH(machInst, (IntRegIndex)vd, 278 rt, index); 279 case 32: 280 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 281 } 282 } else if (bits(b, 1) == 0) { 283 // A8-594 284 return new WarnUnimplemented("vdup", machInst); 285 } 286 } else if (l == 1 && c == 0) { 287 if (a == 0) { 288 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 289 bits(machInst, 7); 290 const IntRegIndex rt = 291 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 292 if (bits(machInst, 20) == 1) { 293 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 294 } else { 295 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 296 } 297 } else if (a == 7) { 298 const IntRegIndex rt = 299 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 300 uint32_t specReg = bits(machInst, 19, 16); 301 switch (specReg) { 302 case 0: 303 specReg = MISCREG_FPSID; 304 break; 305 case 1: 306 specReg = MISCREG_FPSCR; 307 break; 308 case 6: 309 specReg = MISCREG_MVFR1; 310 break; 311 case 7: 312 specReg = MISCREG_MVFR0; 313 break; 314 case 8: 315 specReg = MISCREG_FPEXC; 316 break; 317 default: 318 return new Unknown(machInst); 319 } 320 if (rt == 0xf) { 321 CPSR cpsrMask = 0; 322 cpsrMask.n = 1; 323 cpsrMask.z = 1; 324 cpsrMask.c = 1; 325 cpsrMask.v = 1; 326 return new VmrsApsr(machInst, INTREG_CONDCODES, 327 (IntRegIndex)specReg, (uint32_t)cpsrMask); 328 } else { 329 return new Vmrs(machInst, rt, (IntRegIndex)specReg); 330 } 331 } 332 } else { 333 uint32_t vd = (bits(machInst, 7) << 5) | 334 (bits(machInst, 19, 16) << 1); 335 uint32_t index, size; 336 const IntRegIndex rt = 337 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 338 const bool u = (bits(machInst, 23) == 1); 339 if (bits(machInst, 22) == 1) { 340 size = 8; 341 index = (bits(machInst, 21) << 2) | 342 bits(machInst, 6, 5); 343 } else if (bits(machInst, 5) == 1) { 344 size = 16; 345 index = (bits(machInst, 21) << 1) | 346 bits(machInst, 6); 347 } else if (bits(machInst, 6) == 0 && !u) { 348 size = 32; 349 index = bits(machInst, 21); 350 } else { 351 return new Unknown(machInst); 352 } 353 if (index >= (32 / size)) { 354 index -= (32 / size); 355 vd++; 356 } 357 switch (size) { 358 case 8: 359 if (u) { 360 return new VmovRegCoreUB(machInst, rt, 361 (IntRegIndex)vd, index); 362 } else { 363 return new VmovRegCoreSB(machInst, rt, 364 (IntRegIndex)vd, index); 365 } 366 case 16: 367 if (u) { 368 return new VmovRegCoreUH(machInst, rt, 369 (IntRegIndex)vd, index); 370 } else { 371 return new VmovRegCoreSH(machInst, rt, 372 (IntRegIndex)vd, index); 373 } 374 case 32: 375 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 376 } 377 } 378 return new Unknown(machInst); 379 } 380 ''' 381}}; 382 383def format ShortFpTransfer() {{ 384 decode_block = ''' 385 return decodeShortFpTransfer(machInst); 386 ''' 387}}; 388 389let {{ 390 header_output = ''' 391 StaticInstPtr 392 decodeVfpData(ExtMachInst machInst); 393 ''' 394 decoder_output = ''' 395 StaticInstPtr 396 decodeVfpData(ExtMachInst machInst) 397 { 398 const uint32_t opc1 = bits(machInst, 23, 20); 399 const uint32_t opc2 = bits(machInst, 19, 16); 400 const uint32_t opc3 = bits(machInst, 7, 6); 401 //const uint32_t opc4 = bits(machInst, 3, 0); 402 const bool single = (bits(machInst, 8) == 0); 403 // Used to select between vcmp and vcmpe. 404 const bool e = (bits(machInst, 7) == 1); 405 IntRegIndex vd; 406 IntRegIndex vm; 407 IntRegIndex vn; 408 if (single) { 409 vd = (IntRegIndex)(bits(machInst, 22) | 410 (bits(machInst, 15, 12) << 1)); 411 vm = (IntRegIndex)(bits(machInst, 5) | 412 (bits(machInst, 3, 0) << 1)); 413 vn = (IntRegIndex)(bits(machInst, 7) | 414 (bits(machInst, 19, 16) << 1)); 415 } else { 416 vd = (IntRegIndex)((bits(machInst, 22) << 5) | 417 (bits(machInst, 15, 12) << 1)); 418 vm = (IntRegIndex)((bits(machInst, 5) << 5) | 419 (bits(machInst, 3, 0) << 1)); 420 vn = (IntRegIndex)((bits(machInst, 7) << 5) | 421 (bits(machInst, 19, 16) << 1)); 422 } 423 switch (opc1 & 0xb /* 1011 */) { 424 case 0x0: 425 if (bits(machInst, 6) == 0) { 426 if (single) { 427 return decodeVfpRegRegRegOp<VmlaS>( 428 machInst, vd, vn, vm, false); 429 } else { 430 return decodeVfpRegRegRegOp<VmlaD>( 431 machInst, vd, vn, vm, true); 432 } 433 } else { 434 if (single) { 435 return decodeVfpRegRegRegOp<VmlsS>( 436 machInst, vd, vn, vm, false); 437 } else { 438 return decodeVfpRegRegRegOp<VmlsD>( 439 machInst, vd, vn, vm, true); 440 } 441 } 442 case 0x1: 443 if (bits(machInst, 6) == 1) { 444 if (single) { 445 return decodeVfpRegRegRegOp<VnmlaS>( 446 machInst, vd, vn, vm, false); 447 } else { 448 return decodeVfpRegRegRegOp<VnmlaD>( 449 machInst, vd, vn, vm, true); 450 } 451 } else { 452 if (single) { 453 return decodeVfpRegRegRegOp<VnmlsS>( 454 machInst, vd, vn, vm, false); 455 } else { 456 return decodeVfpRegRegRegOp<VnmlsD>( 457 machInst, vd, vn, vm, true); 458 } 459 } 460 case 0x2: 461 if ((opc3 & 0x1) == 0) { 462 if (single) { 463 return decodeVfpRegRegRegOp<VmulS>( 464 machInst, vd, vn, vm, false); 465 } else { 466 return decodeVfpRegRegRegOp<VmulD>( 467 machInst, vd, vn, vm, true); 468 } 469 } else { 470 if (single) { 471 return decodeVfpRegRegRegOp<VnmulS>( 472 machInst, vd, vn, vm, false); 473 } else { 474 return decodeVfpRegRegRegOp<VnmulD>( 475 machInst, vd, vn, vm, true); 476 } 477 } 478 case 0x3: 479 if ((opc3 & 0x1) == 0) { 480 if (single) { 481 return decodeVfpRegRegRegOp<VaddS>( 482 machInst, vd, vn, vm, false); 483 } else { 484 return decodeVfpRegRegRegOp<VaddD>( 485 machInst, vd, vn, vm, true); 486 } 487 } else { 488 if (single) { 489 return decodeVfpRegRegRegOp<VsubS>( 490 machInst, vd, vn, vm, false); 491 } else { 492 return decodeVfpRegRegRegOp<VsubD>( 493 machInst, vd, vn, vm, true); 494 } 495 } 496 case 0x8: 497 if ((opc3 & 0x1) == 0) { 498 if (single) { 499 return decodeVfpRegRegRegOp<VdivS>( 500 machInst, vd, vn, vm, false); 501 } else { 502 return decodeVfpRegRegRegOp<VdivD>( 503 machInst, vd, vn, vm, true); 504 } 505 } 506 break; 507 case 0xb: 508 if ((opc3 & 0x1) == 0) { 509 const uint32_t baseImm = 510 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 511 if (single) { 512 uint32_t imm = vfp_modified_imm(baseImm, false); 513 return decodeVfpRegImmOp<VmovImmS>( 514 machInst, vd, imm, false); 515 } else { 516 uint64_t imm = vfp_modified_imm(baseImm, true); 517 return decodeVfpRegImmOp<VmovImmD>( 518 machInst, vd, imm, true); 519 } 520 } 521 switch (opc2) { 522 case 0x0: 523 if (opc3 == 1) { 524 if (single) { 525 return decodeVfpRegRegOp<VmovRegS>( 526 machInst, vd, vm, false); 527 } else { 528 return decodeVfpRegRegOp<VmovRegD>( 529 machInst, vd, vm, true); 530 } 531 } else { 532 if (single) { 533 return decodeVfpRegRegOp<VabsS>( 534 machInst, vd, vm, false); 535 } else { 536 return decodeVfpRegRegOp<VabsD>( 537 machInst, vd, vm, true); 538 } 539 } 540 case 0x1: 541 if (opc3 == 1) { 542 if (single) { 543 return decodeVfpRegRegOp<VnegS>( 544 machInst, vd, vm, false); 545 } else { 546 return decodeVfpRegRegOp<VnegD>( 547 machInst, vd, vm, true); 548 } 549 } else { 550 if (single) { 551 return decodeVfpRegRegOp<VsqrtS>( 552 machInst, vd, vm, false); 553 } else { 554 return decodeVfpRegRegOp<VsqrtD>( 555 machInst, vd, vm, true); 556 } 557 } 558 case 0x2: 559 case 0x3: 560 { 561 const bool toHalf = bits(machInst, 16); 562 const bool top = bits(machInst, 7); 563 if (top) { 564 if (toHalf) { 565 return new VcvtFpSFpHT(machInst, vd, vm); 566 } else { 567 return new VcvtFpHTFpS(machInst, vd, vm); 568 } 569 } else { 570 if (toHalf) { 571 return new VcvtFpSFpHB(machInst, vd, vm); 572 } else { 573 return new VcvtFpHBFpS(machInst, vd, vm); 574 } 575 } 576 } 577 case 0x4: 578 if (single) { 579 if (e) { 580 return new VcmpeS(machInst, vd, vm); 581 } else { 582 return new VcmpS(machInst, vd, vm); 583 } 584 } else { 585 if (e) { 586 return new VcmpeD(machInst, vd, vm); 587 } else { 588 return new VcmpD(machInst, vd, vm); 589 } 590 } 591 case 0x5: 592 if (single) { 593 if (e) { 594 return new VcmpeZeroS(machInst, vd, 0); 595 } else { 596 return new VcmpZeroS(machInst, vd, 0); 597 } 598 } else { 599 if (e) { 600 return new VcmpeZeroD(machInst, vd, 0); 601 } else { 602 return new VcmpZeroD(machInst, vd, 0); 603 } 604 } 605 case 0x7: 606 if (opc3 == 0x3) { 607 if (single) { 608 vm = (IntRegIndex)(bits(machInst, 5) | 609 (bits(machInst, 3, 0) << 1)); 610 return new VcvtFpSFpD(machInst, vd, vm); 611 } else { 612 vd = (IntRegIndex)(bits(machInst, 22) | 613 (bits(machInst, 15, 12) << 1)); 614 return new VcvtFpDFpS(machInst, vd, vm); 615 } 616 } 617 break; 618 case 0x8: 619 if (bits(machInst, 7) == 0) { 620 if (single) { 621 return new VcvtUIntFpS(machInst, vd, vm); 622 } else { 623 vm = (IntRegIndex)(bits(machInst, 5) | 624 (bits(machInst, 3, 0) << 1)); 625 return new VcvtUIntFpD(machInst, vd, vm); 626 } 627 } else { 628 if (single) { 629 return new VcvtSIntFpS(machInst, vd, vm); 630 } else { 631 vm = (IntRegIndex)(bits(machInst, 5) | 632 (bits(machInst, 3, 0) << 1)); 633 return new VcvtSIntFpD(machInst, vd, vm); 634 } 635 } 636 case 0xa: 637 { 638 const bool half = (bits(machInst, 7) == 0); 639 const uint32_t imm = bits(machInst, 5) | 640 (bits(machInst, 3, 0) << 1); 641 const uint32_t size = 642 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 643 if (single) { 644 if (half) { 645 return new VcvtSHFixedFpS(machInst, vd, vd, size); 646 } else { 647 return new VcvtSFixedFpS(machInst, vd, vd, size); 648 } 649 } else { 650 if (half) { 651 return new VcvtSHFixedFpD(machInst, vd, vd, size); 652 } else { 653 return new VcvtSFixedFpD(machInst, vd, vd, size); 654 } 655 } 656 } 657 case 0xb: 658 { 659 const bool half = (bits(machInst, 7) == 0); 660 const uint32_t imm = bits(machInst, 5) | 661 (bits(machInst, 3, 0) << 1); 662 const uint32_t size = 663 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 664 if (single) { 665 if (half) { 666 return new VcvtUHFixedFpS(machInst, vd, vd, size); 667 } else { 668 return new VcvtUFixedFpS(machInst, vd, vd, size); 669 } 670 } else { 671 if (half) { 672 return new VcvtUHFixedFpD(machInst, vd, vd, size); 673 } else { 674 return new VcvtUFixedFpD(machInst, vd, vd, size); 675 } 676 } 677 } 678 case 0xc: 679 if (bits(machInst, 7) == 0) { 680 if (single) { 681 return new VcvtFpUIntSR(machInst, vd, vm); 682 } else { 683 vd = (IntRegIndex)(bits(machInst, 22) | 684 (bits(machInst, 15, 12) << 1)); 685 return new VcvtFpUIntDR(machInst, vd, vm); 686 } 687 } else { 688 if (single) { 689 return new VcvtFpUIntS(machInst, vd, vm); 690 } else { 691 vd = (IntRegIndex)(bits(machInst, 22) | 692 (bits(machInst, 15, 12) << 1)); 693 return new VcvtFpUIntD(machInst, vd, vm); 694 } 695 } 696 case 0xd: 697 if (bits(machInst, 7) == 0) { 698 if (single) { 699 return new VcvtFpSIntSR(machInst, vd, vm); 700 } else { 701 vd = (IntRegIndex)(bits(machInst, 22) | 702 (bits(machInst, 15, 12) << 1)); 703 return new VcvtFpSIntDR(machInst, vd, vm); 704 } 705 } else { 706 if (single) { 707 return new VcvtFpSIntS(machInst, vd, vm); 708 } else { 709 vd = (IntRegIndex)(bits(machInst, 22) | 710 (bits(machInst, 15, 12) << 1)); 711 return new VcvtFpSIntD(machInst, vd, vm); 712 } 713 } 714 case 0xe: 715 { 716 const bool half = (bits(machInst, 7) == 0); 717 const uint32_t imm = bits(machInst, 5) | 718 (bits(machInst, 3, 0) << 1); 719 const uint32_t size = 720 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 721 if (single) { 722 if (half) { 723 return new VcvtFpSHFixedS(machInst, vd, vd, size); 724 } else { 725 return new VcvtFpSFixedS(machInst, vd, vd, size); 726 } 727 } else { 728 if (half) { 729 return new VcvtFpSHFixedD(machInst, vd, vd, size); 730 } else { 731 return new VcvtFpSFixedD(machInst, vd, vd, size); 732 } 733 } 734 } 735 case 0xf: 736 { 737 const bool half = (bits(machInst, 7) == 0); 738 const uint32_t imm = bits(machInst, 5) | 739 (bits(machInst, 3, 0) << 1); 740 const uint32_t size = 741 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 742 if (single) { 743 if (half) { 744 return new VcvtFpUHFixedS(machInst, vd, vd, size); 745 } else { 746 return new VcvtFpUFixedS(machInst, vd, vd, size); 747 } 748 } else { 749 if (half) { 750 return new VcvtFpUHFixedD(machInst, vd, vd, size); 751 } else { 752 return new VcvtFpUFixedD(machInst, vd, vd, size); 753 } 754 } 755 } 756 } 757 break; 758 } 759 return new Unknown(machInst); 760 } 761 ''' 762}}; 763 764def format VfpData() {{ 765 decode_block = ''' 766 return decodeVfpData(machInst); 767 ''' 768}};
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