1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48def template FPAExecute {{
49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
50 {
51 Fault fault = NoFault;
52
53 %(fp_enable_check)s;
54
55 %(op_decl)s;
56 %(op_rd)s;
57
58 if (%(predicate_test)s) {
59 %(code)s;
60 if (fault == NoFault) {
61 %(op_wb)s;
62 }
63 }
64
65 return fault;
66 }
67}};
68
69def template FloatDoubleDecode {{
70 {
71 ArmStaticInst *i = NULL;
72 switch (OPCODE_19 << 1 | OPCODE_7)
73 {
74 case 0:
75 i = (ArmStaticInst *)new %(class_name)sS(machInst);
76 break;
77 case 1:
78 i = (ArmStaticInst *)new %(class_name)sD(machInst);
79 break;
80 case 2:
81 case 3:
82 default:
83 panic("Cannot decode float/double nature of the instruction");
84 }
85 return i;
86 }
87}};
88
89// Primary format for float point operate instructions:
90def format FloatOp(code, *flags) {{
91 orig_code = code
92
93 cblk = code
94 iop = InstObjParams(name, Name, 'PredOp',
95 {"code": cblk,
96 "predicate_test": predicateTest},
97 flags)
98 header_output = BasicDeclare.subst(iop)
99 decoder_output = BasicConstructor.subst(iop)
100 exec_output = FPAExecute.subst(iop)
101
102 sng_cblk = code
103 sng_iop = InstObjParams(name, Name+'S', 'PredOp',
104 {"code": sng_cblk,
105 "predicate_test": predicateTest},
106 flags)
107 header_output += BasicDeclare.subst(sng_iop)
108 decoder_output += BasicConstructor.subst(sng_iop)
109 exec_output += FPAExecute.subst(sng_iop)
110
111 dbl_code = re.sub(r'\.sf', '.df', orig_code)
112
113 dbl_cblk = dbl_code
114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
115 {"code": dbl_cblk,
116 "predicate_test": predicateTest},
117 flags)
118 header_output += BasicDeclare.subst(dbl_iop)
119 decoder_output += BasicConstructor.subst(dbl_iop)
120 exec_output += FPAExecute.subst(dbl_iop)
121
122 decode_block = FloatDoubleDecode.subst(iop)
123}};
124
125let {{
126 calcFPCcCode = '''
127 uint16_t _in, _iz, _ic, _iv;
128
129 _in = %(fReg1)s < %(fReg2)s;
130 _iz = %(fReg1)s == %(fReg2)s;
131 _ic = %(fReg1)s >= %(fReg2)s;
132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
133
134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
135 (CondCodes & 0x0FFFFFFF);
136 '''
137}};
138
139def format FloatCmp(fReg1, fReg2, *flags) {{
140 code = calcFPCcCode % vars()
141 iop = InstObjParams(name, Name, 'PredOp',
142 {"code": code,
143 "predicate_test": predicateTest},
144 flags)
145 header_output = BasicDeclare.subst(iop)
146 decoder_output = BasicConstructor.subst(iop)
147 decode_block = BasicDecode.subst(iop)
148 exec_output = FPAExecute.subst(iop)
149}};
150
151let {{
152 header_output = '''
153 StaticInstPtr
154 decodeExtensionRegLoadStore(ExtMachInst machInst);
155 '''
156 decoder_output = '''
157 StaticInstPtr
158 decodeExtensionRegLoadStore(ExtMachInst machInst)
159 {
160 const uint32_t opcode = bits(machInst, 24, 20);
161 const uint32_t offset = bits(machInst, 7, 0);
162 const bool single = (bits(machInst, 8) == 0);
163 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
164 RegIndex vd;
165 if (single) {
166 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
167 bits(machInst, 22));
168 } else {
169 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
170 (bits(machInst, 22) << 5));
171 }
172 switch (bits(opcode, 4, 3)) {
173 case 0x0:
174 if (bits(opcode, 4, 1) == 0x2 &&
175 !(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
176 !(machInst.thumb == 0 && machInst.condCode == 0xf)) {
177 if ((bits(machInst, 7, 4) & 0xd) != 1) {
178 break;
179 }
180 const IntRegIndex rt =
181 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
182 const IntRegIndex rt2 =
183 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
184 const bool op = bits(machInst, 20);
185 uint32_t vm;
186 if (single) {
187 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
188 } else {
189 vm = (bits(machInst, 3, 0) << 1) |
190 (bits(machInst, 5) << 5);
191 }
192 if (op) {
193 return new Vmov2Core2Reg(machInst, rt, rt2,
194 (IntRegIndex)vm);
195 } else {
196 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
197 rt, rt2);
198 }
199 }
200 break;
201 case 0x1:
202 switch (bits(opcode, 1, 0)) {
203 case 0x0:
204 return new VLdmStm(machInst, rn, vd, single,
205 true, false, false, offset);
206 case 0x1:
207 return new VLdmStm(machInst, rn, vd, single,
208 true, false, true, offset);
209 case 0x2:
210 return new VLdmStm(machInst, rn, vd, single,
211 true, true, false, offset);
212 case 0x3:
213 // If rn == sp, then this is called vpop.
214 return new VLdmStm(machInst, rn, vd, single,
215 true, true, true, offset);
216 }
217 case 0x2:
218 if (bits(opcode, 1, 0) == 0x2) {
219 // If rn == sp, then this is called vpush.
220 return new VLdmStm(machInst, rn, vd, single,
221 false, true, false, offset);
222 } else if (bits(opcode, 1, 0) == 0x3) {
223 return new VLdmStm(machInst, rn, vd, single,
224 false, true, true, offset);
225 }
226 // Fall through on purpose
227 case 0x3:
228 const bool up = (bits(machInst, 23) == 1);
229 const uint32_t imm = bits(machInst, 7, 0) << 2;
230 RegIndex vd;
231 if (single) {
232 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
233 (bits(machInst, 22)));
234 } else {
235 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
236 (bits(machInst, 22) << 5));
237 }
238 if (bits(opcode, 1, 0) == 0x0) {
239 if (single) {
240 if (up) {
241 return new %(vstr_us)s(machInst, vd, rn, up, imm);
242 } else {
243 return new %(vstr_s)s(machInst, vd, rn, up, imm);
244 }
245 } else {
246 if (up) {
247 return new %(vstr_ud)s(machInst, vd, vd + 1,
248 rn, up, imm);
249 } else {
250 return new %(vstr_d)s(machInst, vd, vd + 1,
251 rn, up, imm);
252 }
253 }
254 } else if (bits(opcode, 1, 0) == 0x1) {
255 if (single) {
256 if (up) {
257 return new %(vldr_us)s(machInst, vd, rn, up, imm);
258 } else {
259 return new %(vldr_s)s(machInst, vd, rn, up, imm);
260 }
261 } else {
262 if (up) {
263 return new %(vldr_ud)s(machInst, vd, vd + 1,
264 rn, up, imm);
265 } else {
266 return new %(vldr_d)s(machInst, vd, vd + 1,
267 rn, up, imm);
268 }
269 }
270 }
271 }
272 return new Unknown(machInst);
273 }
274 ''' % {
275 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
276 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
277 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
278 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False),
279 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False),
280 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False),
281 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False),
282 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False)
283 }
284}};
285
286def format ExtensionRegLoadStore() {{
287 decode_block = '''
288 return decodeExtensionRegLoadStore(machInst);
289 '''
290}};
291
292let {{
293 header_output = '''
294 StaticInstPtr
295 decodeShortFpTransfer(ExtMachInst machInst);
296 '''
297 decoder_output = '''
298 StaticInstPtr
299 decodeShortFpTransfer(ExtMachInst machInst)
300 {
301 const uint32_t l = bits(machInst, 20);
302 const uint32_t c = bits(machInst, 8);
303 const uint32_t a = bits(machInst, 23, 21);
304 const uint32_t b = bits(machInst, 6, 5);
305 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
306 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
307 return new Unknown(machInst);
308 }
309 if (l == 0 && c == 0) {
310 if (a == 0) {
311 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
312 bits(machInst, 7);
313 const IntRegIndex rt =
314 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
315 if (bits(machInst, 20) == 1) {
316 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
317 } else {
318 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
319 }
320 } else if (a == 0x7) {
321 const IntRegIndex rt =
322 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
323 uint32_t specReg = bits(machInst, 19, 16);
324 switch (specReg) {
325 case 0:
326 specReg = MISCREG_FPSID;
327 break;
328 case 1:
329 specReg = MISCREG_FPSCR;
330 break;
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48def template FPAExecute {{
49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
50 {
51 Fault fault = NoFault;
52
53 %(fp_enable_check)s;
54
55 %(op_decl)s;
56 %(op_rd)s;
57
58 if (%(predicate_test)s) {
59 %(code)s;
60 if (fault == NoFault) {
61 %(op_wb)s;
62 }
63 }
64
65 return fault;
66 }
67}};
68
69def template FloatDoubleDecode {{
70 {
71 ArmStaticInst *i = NULL;
72 switch (OPCODE_19 << 1 | OPCODE_7)
73 {
74 case 0:
75 i = (ArmStaticInst *)new %(class_name)sS(machInst);
76 break;
77 case 1:
78 i = (ArmStaticInst *)new %(class_name)sD(machInst);
79 break;
80 case 2:
81 case 3:
82 default:
83 panic("Cannot decode float/double nature of the instruction");
84 }
85 return i;
86 }
87}};
88
89// Primary format for float point operate instructions:
90def format FloatOp(code, *flags) {{
91 orig_code = code
92
93 cblk = code
94 iop = InstObjParams(name, Name, 'PredOp',
95 {"code": cblk,
96 "predicate_test": predicateTest},
97 flags)
98 header_output = BasicDeclare.subst(iop)
99 decoder_output = BasicConstructor.subst(iop)
100 exec_output = FPAExecute.subst(iop)
101
102 sng_cblk = code
103 sng_iop = InstObjParams(name, Name+'S', 'PredOp',
104 {"code": sng_cblk,
105 "predicate_test": predicateTest},
106 flags)
107 header_output += BasicDeclare.subst(sng_iop)
108 decoder_output += BasicConstructor.subst(sng_iop)
109 exec_output += FPAExecute.subst(sng_iop)
110
111 dbl_code = re.sub(r'\.sf', '.df', orig_code)
112
113 dbl_cblk = dbl_code
114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
115 {"code": dbl_cblk,
116 "predicate_test": predicateTest},
117 flags)
118 header_output += BasicDeclare.subst(dbl_iop)
119 decoder_output += BasicConstructor.subst(dbl_iop)
120 exec_output += FPAExecute.subst(dbl_iop)
121
122 decode_block = FloatDoubleDecode.subst(iop)
123}};
124
125let {{
126 calcFPCcCode = '''
127 uint16_t _in, _iz, _ic, _iv;
128
129 _in = %(fReg1)s < %(fReg2)s;
130 _iz = %(fReg1)s == %(fReg2)s;
131 _ic = %(fReg1)s >= %(fReg2)s;
132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
133
134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
135 (CondCodes & 0x0FFFFFFF);
136 '''
137}};
138
139def format FloatCmp(fReg1, fReg2, *flags) {{
140 code = calcFPCcCode % vars()
141 iop = InstObjParams(name, Name, 'PredOp',
142 {"code": code,
143 "predicate_test": predicateTest},
144 flags)
145 header_output = BasicDeclare.subst(iop)
146 decoder_output = BasicConstructor.subst(iop)
147 decode_block = BasicDecode.subst(iop)
148 exec_output = FPAExecute.subst(iop)
149}};
150
151let {{
152 header_output = '''
153 StaticInstPtr
154 decodeExtensionRegLoadStore(ExtMachInst machInst);
155 '''
156 decoder_output = '''
157 StaticInstPtr
158 decodeExtensionRegLoadStore(ExtMachInst machInst)
159 {
160 const uint32_t opcode = bits(machInst, 24, 20);
161 const uint32_t offset = bits(machInst, 7, 0);
162 const bool single = (bits(machInst, 8) == 0);
163 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
164 RegIndex vd;
165 if (single) {
166 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
167 bits(machInst, 22));
168 } else {
169 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
170 (bits(machInst, 22) << 5));
171 }
172 switch (bits(opcode, 4, 3)) {
173 case 0x0:
174 if (bits(opcode, 4, 1) == 0x2 &&
175 !(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
176 !(machInst.thumb == 0 && machInst.condCode == 0xf)) {
177 if ((bits(machInst, 7, 4) & 0xd) != 1) {
178 break;
179 }
180 const IntRegIndex rt =
181 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
182 const IntRegIndex rt2 =
183 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
184 const bool op = bits(machInst, 20);
185 uint32_t vm;
186 if (single) {
187 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
188 } else {
189 vm = (bits(machInst, 3, 0) << 1) |
190 (bits(machInst, 5) << 5);
191 }
192 if (op) {
193 return new Vmov2Core2Reg(machInst, rt, rt2,
194 (IntRegIndex)vm);
195 } else {
196 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
197 rt, rt2);
198 }
199 }
200 break;
201 case 0x1:
202 switch (bits(opcode, 1, 0)) {
203 case 0x0:
204 return new VLdmStm(machInst, rn, vd, single,
205 true, false, false, offset);
206 case 0x1:
207 return new VLdmStm(machInst, rn, vd, single,
208 true, false, true, offset);
209 case 0x2:
210 return new VLdmStm(machInst, rn, vd, single,
211 true, true, false, offset);
212 case 0x3:
213 // If rn == sp, then this is called vpop.
214 return new VLdmStm(machInst, rn, vd, single,
215 true, true, true, offset);
216 }
217 case 0x2:
218 if (bits(opcode, 1, 0) == 0x2) {
219 // If rn == sp, then this is called vpush.
220 return new VLdmStm(machInst, rn, vd, single,
221 false, true, false, offset);
222 } else if (bits(opcode, 1, 0) == 0x3) {
223 return new VLdmStm(machInst, rn, vd, single,
224 false, true, true, offset);
225 }
226 // Fall through on purpose
227 case 0x3:
228 const bool up = (bits(machInst, 23) == 1);
229 const uint32_t imm = bits(machInst, 7, 0) << 2;
230 RegIndex vd;
231 if (single) {
232 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
233 (bits(machInst, 22)));
234 } else {
235 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
236 (bits(machInst, 22) << 5));
237 }
238 if (bits(opcode, 1, 0) == 0x0) {
239 if (single) {
240 if (up) {
241 return new %(vstr_us)s(machInst, vd, rn, up, imm);
242 } else {
243 return new %(vstr_s)s(machInst, vd, rn, up, imm);
244 }
245 } else {
246 if (up) {
247 return new %(vstr_ud)s(machInst, vd, vd + 1,
248 rn, up, imm);
249 } else {
250 return new %(vstr_d)s(machInst, vd, vd + 1,
251 rn, up, imm);
252 }
253 }
254 } else if (bits(opcode, 1, 0) == 0x1) {
255 if (single) {
256 if (up) {
257 return new %(vldr_us)s(machInst, vd, rn, up, imm);
258 } else {
259 return new %(vldr_s)s(machInst, vd, rn, up, imm);
260 }
261 } else {
262 if (up) {
263 return new %(vldr_ud)s(machInst, vd, vd + 1,
264 rn, up, imm);
265 } else {
266 return new %(vldr_d)s(machInst, vd, vd + 1,
267 rn, up, imm);
268 }
269 }
270 }
271 }
272 return new Unknown(machInst);
273 }
274 ''' % {
275 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
276 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
277 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
278 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False),
279 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False),
280 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False),
281 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False),
282 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False)
283 }
284}};
285
286def format ExtensionRegLoadStore() {{
287 decode_block = '''
288 return decodeExtensionRegLoadStore(machInst);
289 '''
290}};
291
292let {{
293 header_output = '''
294 StaticInstPtr
295 decodeShortFpTransfer(ExtMachInst machInst);
296 '''
297 decoder_output = '''
298 StaticInstPtr
299 decodeShortFpTransfer(ExtMachInst machInst)
300 {
301 const uint32_t l = bits(machInst, 20);
302 const uint32_t c = bits(machInst, 8);
303 const uint32_t a = bits(machInst, 23, 21);
304 const uint32_t b = bits(machInst, 6, 5);
305 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
306 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
307 return new Unknown(machInst);
308 }
309 if (l == 0 && c == 0) {
310 if (a == 0) {
311 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
312 bits(machInst, 7);
313 const IntRegIndex rt =
314 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
315 if (bits(machInst, 20) == 1) {
316 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
317 } else {
318 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
319 }
320 } else if (a == 0x7) {
321 const IntRegIndex rt =
322 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
323 uint32_t specReg = bits(machInst, 19, 16);
324 switch (specReg) {
325 case 0:
326 specReg = MISCREG_FPSID;
327 break;
328 case 1:
329 specReg = MISCREG_FPSCR;
330 break;
|
331 case 8:
332 specReg = MISCREG_FPEXC;
333 break;
334 default:
335 return new Unknown(machInst);
336 }
337 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
338 }
339 } else if (l == 0 && c == 1) {
340 if (bits(a, 2) == 0) {
341 uint32_t vd = (bits(machInst, 7) << 5) |
342 (bits(machInst, 19, 16) << 1);
343 uint32_t index, size;
344 const IntRegIndex rt =
345 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
346 if (bits(machInst, 22) == 1) {
347 size = 8;
348 index = (bits(machInst, 21) << 2) |
349 bits(machInst, 6, 5);
350 } else if (bits(machInst, 5) == 1) {
351 size = 16;
352 index = (bits(machInst, 21) << 1) |
353 bits(machInst, 6);
354 } else if (bits(machInst, 6) == 0) {
355 size = 32;
356 index = bits(machInst, 21);
357 } else {
358 return new Unknown(machInst);
359 }
360 if (index >= (32 / size)) {
361 index -= (32 / size);
362 vd++;
363 }
364 switch (size) {
365 case 8:
366 return new VmovCoreRegB(machInst, (IntRegIndex)vd,
367 rt, index);
368 case 16:
369 return new VmovCoreRegH(machInst, (IntRegIndex)vd,
370 rt, index);
371 case 32:
372 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
373 }
374 } else if (bits(b, 1) == 0) {
375 // A8-594
376 return new WarnUnimplemented("vdup", machInst);
377 }
378 } else if (l == 1 && c == 0) {
379 if (a == 0) {
380 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
381 bits(machInst, 7);
382 const IntRegIndex rt =
383 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
384 if (bits(machInst, 20) == 1) {
385 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
386 } else {
387 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
388 }
389 } else if (a == 7) {
390 const IntRegIndex rt =
391 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
392 uint32_t specReg = bits(machInst, 19, 16);
393 switch (specReg) {
394 case 0:
395 specReg = MISCREG_FPSID;
396 break;
397 case 1:
398 specReg = MISCREG_FPSCR;
399 break;
400 case 6:
401 specReg = MISCREG_MVFR1;
402 break;
403 case 7:
404 specReg = MISCREG_MVFR0;
405 break;
406 case 8:
407 specReg = MISCREG_FPEXC;
408 break;
409 default:
410 return new Unknown(machInst);
411 }
412 if (rt == 0xf) {
413 CPSR cpsrMask = 0;
414 cpsrMask.n = 1;
415 cpsrMask.z = 1;
416 cpsrMask.c = 1;
417 cpsrMask.v = 1;
418 return new VmrsApsr(machInst, INTREG_CONDCODES,
419 (IntRegIndex)specReg, (uint32_t)cpsrMask);
420 } else {
421 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
422 }
423 }
424 } else {
425 uint32_t vd = (bits(machInst, 7) << 5) |
426 (bits(machInst, 19, 16) << 1);
427 uint32_t index, size;
428 const IntRegIndex rt =
429 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
430 const bool u = (bits(machInst, 23) == 1);
431 if (bits(machInst, 22) == 1) {
432 size = 8;
433 index = (bits(machInst, 21) << 2) |
434 bits(machInst, 6, 5);
435 } else if (bits(machInst, 5) == 1) {
436 size = 16;
437 index = (bits(machInst, 21) << 1) |
438 bits(machInst, 6);
439 } else if (bits(machInst, 6) == 0 && !u) {
440 size = 32;
441 index = bits(machInst, 21);
442 } else {
443 return new Unknown(machInst);
444 }
445 if (index >= (32 / size)) {
446 index -= (32 / size);
447 vd++;
448 }
449 switch (size) {
450 case 8:
451 if (u) {
452 return new VmovRegCoreUB(machInst, rt,
453 (IntRegIndex)vd, index);
454 } else {
455 return new VmovRegCoreSB(machInst, rt,
456 (IntRegIndex)vd, index);
457 }
458 case 16:
459 if (u) {
460 return new VmovRegCoreUH(machInst, rt,
461 (IntRegIndex)vd, index);
462 } else {
463 return new VmovRegCoreSH(machInst, rt,
464 (IntRegIndex)vd, index);
465 }
466 case 32:
467 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
468 }
469 }
470 return new Unknown(machInst);
471 }
472 '''
473}};
474
475def format ShortFpTransfer() {{
476 decode_block = '''
477 return decodeShortFpTransfer(machInst);
478 '''
479}};
480
481let {{
482 header_output = '''
483 StaticInstPtr
484 decodeVfpData(ExtMachInst machInst);
485 '''
486 decoder_output = '''
487 StaticInstPtr
488 decodeVfpData(ExtMachInst machInst)
489 {
490 const uint32_t opc1 = bits(machInst, 23, 20);
491 const uint32_t opc2 = bits(machInst, 19, 16);
492 const uint32_t opc3 = bits(machInst, 7, 6);
493 //const uint32_t opc4 = bits(machInst, 3, 0);
494 const bool single = (bits(machInst, 8) == 0);
495 // Used to select between vcmp and vcmpe.
496 const bool e = (bits(machInst, 7) == 1);
497 IntRegIndex vd;
498 IntRegIndex vm;
499 IntRegIndex vn;
500 if (single) {
501 vd = (IntRegIndex)(bits(machInst, 22) |
502 (bits(machInst, 15, 12) << 1));
503 vm = (IntRegIndex)(bits(machInst, 5) |
504 (bits(machInst, 3, 0) << 1));
505 vn = (IntRegIndex)(bits(machInst, 7) |
506 (bits(machInst, 19, 16) << 1));
507 } else {
508 vd = (IntRegIndex)((bits(machInst, 22) << 5) |
509 (bits(machInst, 15, 12) << 1));
510 vm = (IntRegIndex)((bits(machInst, 5) << 5) |
511 (bits(machInst, 3, 0) << 1));
512 vn = (IntRegIndex)((bits(machInst, 7) << 5) |
513 (bits(machInst, 19, 16) << 1));
514 }
515 switch (opc1 & 0xb /* 1011 */) {
516 case 0x0:
517 if (bits(machInst, 6) == 0) {
518 if (single) {
519 return decodeVfpRegRegRegOp<VmlaS>(
520 machInst, vd, vn, vm, false);
521 } else {
522 return decodeVfpRegRegRegOp<VmlaD>(
523 machInst, vd, vn, vm, true);
524 }
525 } else {
526 if (single) {
527 return decodeVfpRegRegRegOp<VmlsS>(
528 machInst, vd, vn, vm, false);
529 } else {
530 return decodeVfpRegRegRegOp<VmlsD>(
531 machInst, vd, vn, vm, true);
532 }
533 }
534 case 0x1:
535 if (bits(machInst, 6) == 1) {
536 if (single) {
537 return decodeVfpRegRegRegOp<VnmlaS>(
538 machInst, vd, vn, vm, false);
539 } else {
540 return decodeVfpRegRegRegOp<VnmlaD>(
541 machInst, vd, vn, vm, true);
542 }
543 } else {
544 if (single) {
545 return decodeVfpRegRegRegOp<VnmlsS>(
546 machInst, vd, vn, vm, false);
547 } else {
548 return decodeVfpRegRegRegOp<VnmlsD>(
549 machInst, vd, vn, vm, true);
550 }
551 }
552 case 0x2:
553 if ((opc3 & 0x1) == 0) {
554 if (single) {
555 return decodeVfpRegRegRegOp<VmulS>(
556 machInst, vd, vn, vm, false);
557 } else {
558 return decodeVfpRegRegRegOp<VmulD>(
559 machInst, vd, vn, vm, true);
560 }
561 } else {
562 if (single) {
563 return decodeVfpRegRegRegOp<VnmulS>(
564 machInst, vd, vn, vm, false);
565 } else {
566 return decodeVfpRegRegRegOp<VnmulD>(
567 machInst, vd, vn, vm, true);
568 }
569 }
570 case 0x3:
571 if ((opc3 & 0x1) == 0) {
572 if (single) {
573 return decodeVfpRegRegRegOp<VaddS>(
574 machInst, vd, vn, vm, false);
575 } else {
576 return decodeVfpRegRegRegOp<VaddD>(
577 machInst, vd, vn, vm, true);
578 }
579 } else {
580 if (single) {
581 return decodeVfpRegRegRegOp<VsubS>(
582 machInst, vd, vn, vm, false);
583 } else {
584 return decodeVfpRegRegRegOp<VsubD>(
585 machInst, vd, vn, vm, true);
586 }
587 }
588 case 0x8:
589 if ((opc3 & 0x1) == 0) {
590 if (single) {
591 return decodeVfpRegRegRegOp<VdivS>(
592 machInst, vd, vn, vm, false);
593 } else {
594 return decodeVfpRegRegRegOp<VdivD>(
595 machInst, vd, vn, vm, true);
596 }
597 }
598 break;
599 case 0xb:
600 if ((opc3 & 0x1) == 0) {
601 const uint32_t baseImm =
602 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
603 if (single) {
604 uint32_t imm = vfp_modified_imm(baseImm, false);
605 return decodeVfpRegImmOp<VmovImmS>(
606 machInst, vd, imm, false);
607 } else {
608 uint64_t imm = vfp_modified_imm(baseImm, true);
609 return decodeVfpRegImmOp<VmovImmD>(
610 machInst, vd, imm, true);
611 }
612 }
613 switch (opc2) {
614 case 0x0:
615 if (opc3 == 1) {
616 if (single) {
617 return decodeVfpRegRegOp<VmovRegS>(
618 machInst, vd, vm, false);
619 } else {
620 return decodeVfpRegRegOp<VmovRegD>(
621 machInst, vd, vm, true);
622 }
623 } else {
624 if (single) {
625 return decodeVfpRegRegOp<VabsS>(
626 machInst, vd, vm, false);
627 } else {
628 return decodeVfpRegRegOp<VabsD>(
629 machInst, vd, vm, true);
630 }
631 }
632 case 0x1:
633 if (opc3 == 1) {
634 if (single) {
635 return decodeVfpRegRegOp<VnegS>(
636 machInst, vd, vm, false);
637 } else {
638 return decodeVfpRegRegOp<VnegD>(
639 machInst, vd, vm, true);
640 }
641 } else {
642 if (single) {
643 return decodeVfpRegRegOp<VsqrtS>(
644 machInst, vd, vm, false);
645 } else {
646 return decodeVfpRegRegOp<VsqrtD>(
647 machInst, vd, vm, true);
648 }
649 }
650 case 0x2:
651 case 0x3:
652 // Between half and single precision.
653 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
654 case 0x4:
655 if (single) {
656 if (e) {
657 return new VcmpeS(machInst, vd, vm);
658 } else {
659 return new VcmpS(machInst, vd, vm);
660 }
661 } else {
662 if (e) {
663 return new VcmpeD(machInst, vd, vm);
664 } else {
665 return new VcmpD(machInst, vd, vm);
666 }
667 }
668 case 0x5:
669 if (single) {
670 if (e) {
671 return new VcmpeZeroS(machInst, vd, 0);
672 } else {
673 return new VcmpZeroS(machInst, vd, 0);
674 }
675 } else {
676 if (e) {
677 return new VcmpeZeroD(machInst, vd, 0);
678 } else {
679 return new VcmpZeroD(machInst, vd, 0);
680 }
681 }
682 case 0x7:
683 if (opc3 == 0x3) {
684 if (single) {
685 vm = (IntRegIndex)(bits(machInst, 5) |
686 (bits(machInst, 3, 0) << 1));
687 return new VcvtFpSFpD(machInst, vd, vm);
688 } else {
689 vd = (IntRegIndex)(bits(machInst, 22) |
690 (bits(machInst, 15, 12) << 1));
691 return new VcvtFpDFpS(machInst, vd, vm);
692 }
693 }
694 break;
695 case 0x8:
696 if (bits(machInst, 7) == 0) {
697 if (single) {
698 return new VcvtUIntFpS(machInst, vd, vm);
699 } else {
700 vm = (IntRegIndex)(bits(machInst, 5) |
701 (bits(machInst, 3, 0) << 1));
702 return new VcvtUIntFpD(machInst, vd, vm);
703 }
704 } else {
705 if (single) {
706 return new VcvtSIntFpS(machInst, vd, vm);
707 } else {
708 vm = (IntRegIndex)(bits(machInst, 5) |
709 (bits(machInst, 3, 0) << 1));
710 return new VcvtSIntFpD(machInst, vd, vm);
711 }
712 }
713 case 0xa:
714 {
715 const bool half = (bits(machInst, 7) == 0);
716 const uint32_t imm = bits(machInst, 5) |
717 (bits(machInst, 3, 0) << 1);
718 const uint32_t size =
719 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
720 if (single) {
721 if (half) {
722 return new VcvtSHFixedFpS(machInst, vd, vd, size);
723 } else {
724 return new VcvtSFixedFpS(machInst, vd, vd, size);
725 }
726 } else {
727 if (half) {
728 return new VcvtSHFixedFpD(machInst, vd, vd, size);
729 } else {
730 return new VcvtSFixedFpD(machInst, vd, vd, size);
731 }
732 }
733 }
734 case 0xb:
735 {
736 const bool half = (bits(machInst, 7) == 0);
737 const uint32_t imm = bits(machInst, 5) |
738 (bits(machInst, 3, 0) << 1);
739 const uint32_t size =
740 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
741 if (single) {
742 if (half) {
743 return new VcvtUHFixedFpS(machInst, vd, vd, size);
744 } else {
745 return new VcvtUFixedFpS(machInst, vd, vd, size);
746 }
747 } else {
748 if (half) {
749 return new VcvtUHFixedFpD(machInst, vd, vd, size);
750 } else {
751 return new VcvtUFixedFpD(machInst, vd, vd, size);
752 }
753 }
754 }
755 case 0xc:
756 if (bits(machInst, 7) == 0) {
757 if (single) {
758 return new VcvtFpUIntSR(machInst, vd, vm);
759 } else {
760 vd = (IntRegIndex)(bits(machInst, 22) |
761 (bits(machInst, 15, 12) << 1));
762 return new VcvtFpUIntDR(machInst, vd, vm);
763 }
764 } else {
765 if (single) {
766 return new VcvtFpUIntS(machInst, vd, vm);
767 } else {
768 vd = (IntRegIndex)(bits(machInst, 22) |
769 (bits(machInst, 15, 12) << 1));
770 return new VcvtFpUIntD(machInst, vd, vm);
771 }
772 }
773 case 0xd:
774 if (bits(machInst, 7) == 0) {
775 if (single) {
776 return new VcvtFpSIntSR(machInst, vd, vm);
777 } else {
778 vd = (IntRegIndex)(bits(machInst, 22) |
779 (bits(machInst, 15, 12) << 1));
780 return new VcvtFpSIntDR(machInst, vd, vm);
781 }
782 } else {
783 if (single) {
784 return new VcvtFpSIntS(machInst, vd, vm);
785 } else {
786 vd = (IntRegIndex)(bits(machInst, 22) |
787 (bits(machInst, 15, 12) << 1));
788 return new VcvtFpSIntD(machInst, vd, vm);
789 }
790 }
791 case 0xe:
792 {
793 const bool half = (bits(machInst, 7) == 0);
794 const uint32_t imm = bits(machInst, 5) |
795 (bits(machInst, 3, 0) << 1);
796 const uint32_t size =
797 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
798 if (single) {
799 if (half) {
800 return new VcvtFpSHFixedS(machInst, vd, vd, size);
801 } else {
802 return new VcvtFpSFixedS(machInst, vd, vd, size);
803 }
804 } else {
805 if (half) {
806 return new VcvtFpSHFixedD(machInst, vd, vd, size);
807 } else {
808 return new VcvtFpSFixedD(machInst, vd, vd, size);
809 }
810 }
811 }
812 case 0xf:
813 {
814 const bool half = (bits(machInst, 7) == 0);
815 const uint32_t imm = bits(machInst, 5) |
816 (bits(machInst, 3, 0) << 1);
817 const uint32_t size =
818 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
819 if (single) {
820 if (half) {
821 return new VcvtFpUHFixedS(machInst, vd, vd, size);
822 } else {
823 return new VcvtFpUFixedS(machInst, vd, vd, size);
824 }
825 } else {
826 if (half) {
827 return new VcvtFpUHFixedD(machInst, vd, vd, size);
828 } else {
829 return new VcvtFpUFixedD(machInst, vd, vd, size);
830 }
831 }
832 }
833 }
834 break;
835 }
836 return new Unknown(machInst);
837 }
838 '''
839}};
840
841def format VfpData() {{
842 decode_block = '''
843 return decodeVfpData(machInst);
844 '''
845}};
| 337 case 8:
338 specReg = MISCREG_FPEXC;
339 break;
340 default:
341 return new Unknown(machInst);
342 }
343 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
344 }
345 } else if (l == 0 && c == 1) {
346 if (bits(a, 2) == 0) {
347 uint32_t vd = (bits(machInst, 7) << 5) |
348 (bits(machInst, 19, 16) << 1);
349 uint32_t index, size;
350 const IntRegIndex rt =
351 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
352 if (bits(machInst, 22) == 1) {
353 size = 8;
354 index = (bits(machInst, 21) << 2) |
355 bits(machInst, 6, 5);
356 } else if (bits(machInst, 5) == 1) {
357 size = 16;
358 index = (bits(machInst, 21) << 1) |
359 bits(machInst, 6);
360 } else if (bits(machInst, 6) == 0) {
361 size = 32;
362 index = bits(machInst, 21);
363 } else {
364 return new Unknown(machInst);
365 }
366 if (index >= (32 / size)) {
367 index -= (32 / size);
368 vd++;
369 }
370 switch (size) {
371 case 8:
372 return new VmovCoreRegB(machInst, (IntRegIndex)vd,
373 rt, index);
374 case 16:
375 return new VmovCoreRegH(machInst, (IntRegIndex)vd,
376 rt, index);
377 case 32:
378 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
379 }
380 } else if (bits(b, 1) == 0) {
381 // A8-594
382 return new WarnUnimplemented("vdup", machInst);
383 }
384 } else if (l == 1 && c == 0) {
385 if (a == 0) {
386 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
387 bits(machInst, 7);
388 const IntRegIndex rt =
389 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
390 if (bits(machInst, 20) == 1) {
391 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
392 } else {
393 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
394 }
395 } else if (a == 7) {
396 const IntRegIndex rt =
397 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
398 uint32_t specReg = bits(machInst, 19, 16);
399 switch (specReg) {
400 case 0:
401 specReg = MISCREG_FPSID;
402 break;
403 case 1:
404 specReg = MISCREG_FPSCR;
405 break;
406 case 6:
407 specReg = MISCREG_MVFR1;
408 break;
409 case 7:
410 specReg = MISCREG_MVFR0;
411 break;
412 case 8:
413 specReg = MISCREG_FPEXC;
414 break;
415 default:
416 return new Unknown(machInst);
417 }
418 if (rt == 0xf) {
419 CPSR cpsrMask = 0;
420 cpsrMask.n = 1;
421 cpsrMask.z = 1;
422 cpsrMask.c = 1;
423 cpsrMask.v = 1;
424 return new VmrsApsr(machInst, INTREG_CONDCODES,
425 (IntRegIndex)specReg, (uint32_t)cpsrMask);
426 } else {
427 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
428 }
429 }
430 } else {
431 uint32_t vd = (bits(machInst, 7) << 5) |
432 (bits(machInst, 19, 16) << 1);
433 uint32_t index, size;
434 const IntRegIndex rt =
435 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
436 const bool u = (bits(machInst, 23) == 1);
437 if (bits(machInst, 22) == 1) {
438 size = 8;
439 index = (bits(machInst, 21) << 2) |
440 bits(machInst, 6, 5);
441 } else if (bits(machInst, 5) == 1) {
442 size = 16;
443 index = (bits(machInst, 21) << 1) |
444 bits(machInst, 6);
445 } else if (bits(machInst, 6) == 0 && !u) {
446 size = 32;
447 index = bits(machInst, 21);
448 } else {
449 return new Unknown(machInst);
450 }
451 if (index >= (32 / size)) {
452 index -= (32 / size);
453 vd++;
454 }
455 switch (size) {
456 case 8:
457 if (u) {
458 return new VmovRegCoreUB(machInst, rt,
459 (IntRegIndex)vd, index);
460 } else {
461 return new VmovRegCoreSB(machInst, rt,
462 (IntRegIndex)vd, index);
463 }
464 case 16:
465 if (u) {
466 return new VmovRegCoreUH(machInst, rt,
467 (IntRegIndex)vd, index);
468 } else {
469 return new VmovRegCoreSH(machInst, rt,
470 (IntRegIndex)vd, index);
471 }
472 case 32:
473 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
474 }
475 }
476 return new Unknown(machInst);
477 }
478 '''
479}};
480
481def format ShortFpTransfer() {{
482 decode_block = '''
483 return decodeShortFpTransfer(machInst);
484 '''
485}};
486
487let {{
488 header_output = '''
489 StaticInstPtr
490 decodeVfpData(ExtMachInst machInst);
491 '''
492 decoder_output = '''
493 StaticInstPtr
494 decodeVfpData(ExtMachInst machInst)
495 {
496 const uint32_t opc1 = bits(machInst, 23, 20);
497 const uint32_t opc2 = bits(machInst, 19, 16);
498 const uint32_t opc3 = bits(machInst, 7, 6);
499 //const uint32_t opc4 = bits(machInst, 3, 0);
500 const bool single = (bits(machInst, 8) == 0);
501 // Used to select between vcmp and vcmpe.
502 const bool e = (bits(machInst, 7) == 1);
503 IntRegIndex vd;
504 IntRegIndex vm;
505 IntRegIndex vn;
506 if (single) {
507 vd = (IntRegIndex)(bits(machInst, 22) |
508 (bits(machInst, 15, 12) << 1));
509 vm = (IntRegIndex)(bits(machInst, 5) |
510 (bits(machInst, 3, 0) << 1));
511 vn = (IntRegIndex)(bits(machInst, 7) |
512 (bits(machInst, 19, 16) << 1));
513 } else {
514 vd = (IntRegIndex)((bits(machInst, 22) << 5) |
515 (bits(machInst, 15, 12) << 1));
516 vm = (IntRegIndex)((bits(machInst, 5) << 5) |
517 (bits(machInst, 3, 0) << 1));
518 vn = (IntRegIndex)((bits(machInst, 7) << 5) |
519 (bits(machInst, 19, 16) << 1));
520 }
521 switch (opc1 & 0xb /* 1011 */) {
522 case 0x0:
523 if (bits(machInst, 6) == 0) {
524 if (single) {
525 return decodeVfpRegRegRegOp<VmlaS>(
526 machInst, vd, vn, vm, false);
527 } else {
528 return decodeVfpRegRegRegOp<VmlaD>(
529 machInst, vd, vn, vm, true);
530 }
531 } else {
532 if (single) {
533 return decodeVfpRegRegRegOp<VmlsS>(
534 machInst, vd, vn, vm, false);
535 } else {
536 return decodeVfpRegRegRegOp<VmlsD>(
537 machInst, vd, vn, vm, true);
538 }
539 }
540 case 0x1:
541 if (bits(machInst, 6) == 1) {
542 if (single) {
543 return decodeVfpRegRegRegOp<VnmlaS>(
544 machInst, vd, vn, vm, false);
545 } else {
546 return decodeVfpRegRegRegOp<VnmlaD>(
547 machInst, vd, vn, vm, true);
548 }
549 } else {
550 if (single) {
551 return decodeVfpRegRegRegOp<VnmlsS>(
552 machInst, vd, vn, vm, false);
553 } else {
554 return decodeVfpRegRegRegOp<VnmlsD>(
555 machInst, vd, vn, vm, true);
556 }
557 }
558 case 0x2:
559 if ((opc3 & 0x1) == 0) {
560 if (single) {
561 return decodeVfpRegRegRegOp<VmulS>(
562 machInst, vd, vn, vm, false);
563 } else {
564 return decodeVfpRegRegRegOp<VmulD>(
565 machInst, vd, vn, vm, true);
566 }
567 } else {
568 if (single) {
569 return decodeVfpRegRegRegOp<VnmulS>(
570 machInst, vd, vn, vm, false);
571 } else {
572 return decodeVfpRegRegRegOp<VnmulD>(
573 machInst, vd, vn, vm, true);
574 }
575 }
576 case 0x3:
577 if ((opc3 & 0x1) == 0) {
578 if (single) {
579 return decodeVfpRegRegRegOp<VaddS>(
580 machInst, vd, vn, vm, false);
581 } else {
582 return decodeVfpRegRegRegOp<VaddD>(
583 machInst, vd, vn, vm, true);
584 }
585 } else {
586 if (single) {
587 return decodeVfpRegRegRegOp<VsubS>(
588 machInst, vd, vn, vm, false);
589 } else {
590 return decodeVfpRegRegRegOp<VsubD>(
591 machInst, vd, vn, vm, true);
592 }
593 }
594 case 0x8:
595 if ((opc3 & 0x1) == 0) {
596 if (single) {
597 return decodeVfpRegRegRegOp<VdivS>(
598 machInst, vd, vn, vm, false);
599 } else {
600 return decodeVfpRegRegRegOp<VdivD>(
601 machInst, vd, vn, vm, true);
602 }
603 }
604 break;
605 case 0xb:
606 if ((opc3 & 0x1) == 0) {
607 const uint32_t baseImm =
608 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
609 if (single) {
610 uint32_t imm = vfp_modified_imm(baseImm, false);
611 return decodeVfpRegImmOp<VmovImmS>(
612 machInst, vd, imm, false);
613 } else {
614 uint64_t imm = vfp_modified_imm(baseImm, true);
615 return decodeVfpRegImmOp<VmovImmD>(
616 machInst, vd, imm, true);
617 }
618 }
619 switch (opc2) {
620 case 0x0:
621 if (opc3 == 1) {
622 if (single) {
623 return decodeVfpRegRegOp<VmovRegS>(
624 machInst, vd, vm, false);
625 } else {
626 return decodeVfpRegRegOp<VmovRegD>(
627 machInst, vd, vm, true);
628 }
629 } else {
630 if (single) {
631 return decodeVfpRegRegOp<VabsS>(
632 machInst, vd, vm, false);
633 } else {
634 return decodeVfpRegRegOp<VabsD>(
635 machInst, vd, vm, true);
636 }
637 }
638 case 0x1:
639 if (opc3 == 1) {
640 if (single) {
641 return decodeVfpRegRegOp<VnegS>(
642 machInst, vd, vm, false);
643 } else {
644 return decodeVfpRegRegOp<VnegD>(
645 machInst, vd, vm, true);
646 }
647 } else {
648 if (single) {
649 return decodeVfpRegRegOp<VsqrtS>(
650 machInst, vd, vm, false);
651 } else {
652 return decodeVfpRegRegOp<VsqrtD>(
653 machInst, vd, vm, true);
654 }
655 }
656 case 0x2:
657 case 0x3:
658 // Between half and single precision.
659 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
660 case 0x4:
661 if (single) {
662 if (e) {
663 return new VcmpeS(machInst, vd, vm);
664 } else {
665 return new VcmpS(machInst, vd, vm);
666 }
667 } else {
668 if (e) {
669 return new VcmpeD(machInst, vd, vm);
670 } else {
671 return new VcmpD(machInst, vd, vm);
672 }
673 }
674 case 0x5:
675 if (single) {
676 if (e) {
677 return new VcmpeZeroS(machInst, vd, 0);
678 } else {
679 return new VcmpZeroS(machInst, vd, 0);
680 }
681 } else {
682 if (e) {
683 return new VcmpeZeroD(machInst, vd, 0);
684 } else {
685 return new VcmpZeroD(machInst, vd, 0);
686 }
687 }
688 case 0x7:
689 if (opc3 == 0x3) {
690 if (single) {
691 vm = (IntRegIndex)(bits(machInst, 5) |
692 (bits(machInst, 3, 0) << 1));
693 return new VcvtFpSFpD(machInst, vd, vm);
694 } else {
695 vd = (IntRegIndex)(bits(machInst, 22) |
696 (bits(machInst, 15, 12) << 1));
697 return new VcvtFpDFpS(machInst, vd, vm);
698 }
699 }
700 break;
701 case 0x8:
702 if (bits(machInst, 7) == 0) {
703 if (single) {
704 return new VcvtUIntFpS(machInst, vd, vm);
705 } else {
706 vm = (IntRegIndex)(bits(machInst, 5) |
707 (bits(machInst, 3, 0) << 1));
708 return new VcvtUIntFpD(machInst, vd, vm);
709 }
710 } else {
711 if (single) {
712 return new VcvtSIntFpS(machInst, vd, vm);
713 } else {
714 vm = (IntRegIndex)(bits(machInst, 5) |
715 (bits(machInst, 3, 0) << 1));
716 return new VcvtSIntFpD(machInst, vd, vm);
717 }
718 }
719 case 0xa:
720 {
721 const bool half = (bits(machInst, 7) == 0);
722 const uint32_t imm = bits(machInst, 5) |
723 (bits(machInst, 3, 0) << 1);
724 const uint32_t size =
725 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
726 if (single) {
727 if (half) {
728 return new VcvtSHFixedFpS(machInst, vd, vd, size);
729 } else {
730 return new VcvtSFixedFpS(machInst, vd, vd, size);
731 }
732 } else {
733 if (half) {
734 return new VcvtSHFixedFpD(machInst, vd, vd, size);
735 } else {
736 return new VcvtSFixedFpD(machInst, vd, vd, size);
737 }
738 }
739 }
740 case 0xb:
741 {
742 const bool half = (bits(machInst, 7) == 0);
743 const uint32_t imm = bits(machInst, 5) |
744 (bits(machInst, 3, 0) << 1);
745 const uint32_t size =
746 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
747 if (single) {
748 if (half) {
749 return new VcvtUHFixedFpS(machInst, vd, vd, size);
750 } else {
751 return new VcvtUFixedFpS(machInst, vd, vd, size);
752 }
753 } else {
754 if (half) {
755 return new VcvtUHFixedFpD(machInst, vd, vd, size);
756 } else {
757 return new VcvtUFixedFpD(machInst, vd, vd, size);
758 }
759 }
760 }
761 case 0xc:
762 if (bits(machInst, 7) == 0) {
763 if (single) {
764 return new VcvtFpUIntSR(machInst, vd, vm);
765 } else {
766 vd = (IntRegIndex)(bits(machInst, 22) |
767 (bits(machInst, 15, 12) << 1));
768 return new VcvtFpUIntDR(machInst, vd, vm);
769 }
770 } else {
771 if (single) {
772 return new VcvtFpUIntS(machInst, vd, vm);
773 } else {
774 vd = (IntRegIndex)(bits(machInst, 22) |
775 (bits(machInst, 15, 12) << 1));
776 return new VcvtFpUIntD(machInst, vd, vm);
777 }
778 }
779 case 0xd:
780 if (bits(machInst, 7) == 0) {
781 if (single) {
782 return new VcvtFpSIntSR(machInst, vd, vm);
783 } else {
784 vd = (IntRegIndex)(bits(machInst, 22) |
785 (bits(machInst, 15, 12) << 1));
786 return new VcvtFpSIntDR(machInst, vd, vm);
787 }
788 } else {
789 if (single) {
790 return new VcvtFpSIntS(machInst, vd, vm);
791 } else {
792 vd = (IntRegIndex)(bits(machInst, 22) |
793 (bits(machInst, 15, 12) << 1));
794 return new VcvtFpSIntD(machInst, vd, vm);
795 }
796 }
797 case 0xe:
798 {
799 const bool half = (bits(machInst, 7) == 0);
800 const uint32_t imm = bits(machInst, 5) |
801 (bits(machInst, 3, 0) << 1);
802 const uint32_t size =
803 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
804 if (single) {
805 if (half) {
806 return new VcvtFpSHFixedS(machInst, vd, vd, size);
807 } else {
808 return new VcvtFpSFixedS(machInst, vd, vd, size);
809 }
810 } else {
811 if (half) {
812 return new VcvtFpSHFixedD(machInst, vd, vd, size);
813 } else {
814 return new VcvtFpSFixedD(machInst, vd, vd, size);
815 }
816 }
817 }
818 case 0xf:
819 {
820 const bool half = (bits(machInst, 7) == 0);
821 const uint32_t imm = bits(machInst, 5) |
822 (bits(machInst, 3, 0) << 1);
823 const uint32_t size =
824 (bits(machInst, 7) == 0 ? 16 : 32) - imm;
825 if (single) {
826 if (half) {
827 return new VcvtFpUHFixedS(machInst, vd, vd, size);
828 } else {
829 return new VcvtFpUFixedS(machInst, vd, vd, size);
830 }
831 } else {
832 if (half) {
833 return new VcvtFpUHFixedD(machInst, vd, vd, size);
834 } else {
835 return new VcvtFpUFixedD(machInst, vd, vd, size);
836 }
837 }
838 }
839 }
840 break;
841 }
842 return new Unknown(machInst);
843 }
844 '''
845}};
846
847def format VfpData() {{
848 decode_block = '''
849 return decodeVfpData(machInst);
850 '''
851}};
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