1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48def template FPAExecute {{
49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
50 {
51 Fault fault = NoFault;
52
53 %(fp_enable_check)s;
54
55 %(op_decl)s;
56 %(op_rd)s;
57
58 if (%(predicate_test)s) {
59 %(code)s;
60 if (fault == NoFault) {
61 %(op_wb)s;
62 }
63 }
64
65 return fault;
66 }
67}};
68
69def template FloatDoubleDecode {{
70 {
71 ArmStaticInst *i = NULL;
72 switch (OPCODE_19 << 1 | OPCODE_7)
73 {
74 case 0:
75 i = (ArmStaticInst *)new %(class_name)sS(machInst);
76 break;
77 case 1:
78 i = (ArmStaticInst *)new %(class_name)sD(machInst);
79 break;
80 case 2:
81 case 3:
82 default:
83 panic("Cannot decode float/double nature of the instruction");
84 }
85 return i;
86 }
87}};
88
89// Primary format for float point operate instructions:
90def format FloatOp(code, *flags) {{
91 orig_code = code
92
93 cblk = code
94 iop = InstObjParams(name, Name, 'PredOp',
95 {"code": cblk,
96 "predicate_test": predicateTest},
97 flags)
98 header_output = BasicDeclare.subst(iop)
99 decoder_output = BasicConstructor.subst(iop)
100 exec_output = FPAExecute.subst(iop)
101
102 sng_cblk = code
103 sng_iop = InstObjParams(name, Name+'S', 'PredOp',
104 {"code": sng_cblk,
105 "predicate_test": predicateTest},
106 flags)
107 header_output += BasicDeclare.subst(sng_iop)
108 decoder_output += BasicConstructor.subst(sng_iop)
109 exec_output += FPAExecute.subst(sng_iop)
110
111 dbl_code = re.sub(r'\.sf', '.df', orig_code)
112
113 dbl_cblk = dbl_code
114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
115 {"code": dbl_cblk,
116 "predicate_test": predicateTest},
117 flags)
118 header_output += BasicDeclare.subst(dbl_iop)
119 decoder_output += BasicConstructor.subst(dbl_iop)
120 exec_output += FPAExecute.subst(dbl_iop)
121
122 decode_block = FloatDoubleDecode.subst(iop)
123}};
124
125let {{
126 calcFPCcCode = '''
127 uint16_t _in, _iz, _ic, _iv;
128
129 _in = %(fReg1)s < %(fReg2)s;
130 _iz = %(fReg1)s == %(fReg2)s;
131 _ic = %(fReg1)s >= %(fReg2)s;
132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
133
134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
135 (CondCodes & 0x0FFFFFFF);
136 '''
137}};
138
139def format FloatCmp(fReg1, fReg2, *flags) {{
140 code = calcFPCcCode % vars()
141 iop = InstObjParams(name, Name, 'PredOp',
142 {"code": code,
143 "predicate_test": predicateTest},
144 flags)
145 header_output = BasicDeclare.subst(iop)
146 decoder_output = BasicConstructor.subst(iop)
147 decode_block = BasicDecode.subst(iop)
148 exec_output = FPAExecute.subst(iop)
149}};
150
151let {{
152 header_output = '''
153 StaticInstPtr
154 decodeExtensionRegLoadStore(ExtMachInst machInst);
155 '''
156 decoder_output = '''
157 StaticInstPtr
158 decodeExtensionRegLoadStore(ExtMachInst machInst)
159 {
160 const uint32_t opcode = bits(machInst, 24, 20);
161 const uint32_t offset = bits(machInst, 7, 0);
162 const bool single = (bits(machInst, 8) == 0);
163 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
164 RegIndex vd;
165 if (single) {
166 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
167 bits(machInst, 22));
168 } else {
169 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
170 (bits(machInst, 22) << 5));
171 }
172 switch (bits(opcode, 4, 3)) {
173 case 0x0:
174 if (bits(opcode, 4, 1) == 0x2 &&
175 !(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
176 !(machInst.thumb == 0 && machInst.condCode == 0xf)) {
177 if ((bits(machInst, 7, 4) & 0xd) != 1) {
178 break;
179 }
180 const IntRegIndex rt =
181 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
182 const IntRegIndex rt2 =
183 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
184 const bool op = bits(machInst, 20);
185 uint32_t vm;
186 if (single) {
187 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
188 } else {
189 vm = (bits(machInst, 3, 0) << 1) |
190 (bits(machInst, 5) << 5);
191 }
192 if (op) {
193 return new Vmov2Core2Reg(machInst, rt, rt2,
194 (IntRegIndex)vm);
195 } else {
196 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
197 rt, rt2);
198 }
199 }
200 break;
201 case 0x1:
202 switch (bits(opcode, 1, 0)) {
203 case 0x0:
204 return new VLdmStm(machInst, rn, vd, single,
205 true, false, false, offset);
206 case 0x1:
207 return new VLdmStm(machInst, rn, vd, single,
208 true, false, true, offset);
209 case 0x2:
210 return new VLdmStm(machInst, rn, vd, single,
211 true, true, false, offset);
212 case 0x3:
213 // If rn == sp, then this is called vpop.
214 return new VLdmStm(machInst, rn, vd, single,
215 true, true, true, offset);
216 }
217 case 0x2:
218 if (bits(opcode, 1, 0) == 0x2) {
219 // If rn == sp, then this is called vpush.
220 return new VLdmStm(machInst, rn, vd, single,
221 false, true, false, offset);
222 } else if (bits(opcode, 1, 0) == 0x3) {
223 return new VLdmStm(machInst, rn, vd, single,
224 false, true, true, offset);
225 }
226 // Fall through on purpose
227 case 0x3:
228 const bool up = (bits(machInst, 23) == 1);
229 const uint32_t imm = bits(machInst, 7, 0) << 2;
230 RegIndex vd;
231 if (single) {
232 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
233 (bits(machInst, 22)));
234 } else {
235 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
236 (bits(machInst, 22) << 5));
237 }
238 if (bits(opcode, 1, 0) == 0x0) {
239 if (single) {
240 if (up) {
241 return new %(vstr_us)s(machInst, vd, rn, up, imm);
242 } else {
243 return new %(vstr_s)s(machInst, vd, rn, up, imm);
244 }
245 } else {
246 if (up) {
247 return new %(vstr_ud)s(machInst, vd, vd + 1,
248 rn, up, imm);
249 } else {
250 return new %(vstr_d)s(machInst, vd, vd + 1,
251 rn, up, imm);
252 }
253 }
254 } else if (bits(opcode, 1, 0) == 0x1) {
255 if (single) {
256 if (up) {
257 return new %(vldr_us)s(machInst, vd, rn, up, imm);
258 } else {
259 return new %(vldr_s)s(machInst, vd, rn, up, imm);
260 }
261 } else {
262 if (up) {
263 return new %(vldr_ud)s(machInst, vd, vd + 1,
264 rn, up, imm);
265 } else {
266 return new %(vldr_d)s(machInst, vd, vd + 1,
267 rn, up, imm);
268 }
269 }
270 }
271 }
272 return new Unknown(machInst);
273 }
274 ''' % {
275 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
276 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
277 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
278 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False),
279 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False),
280 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False),
281 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False),
282 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False)
283 }
284}};
285
286def format ExtensionRegLoadStore() {{
287 decode_block = '''
288 return decodeExtensionRegLoadStore(machInst);
289 '''
290}};
291
292let {{
293 header_output = '''
294 StaticInstPtr
295 decodeShortFpTransfer(ExtMachInst machInst);
296 '''
297 decoder_output = '''
298 StaticInstPtr
299 decodeShortFpTransfer(ExtMachInst machInst)
300 {
301 const uint32_t l = bits(machInst, 20);
302 const uint32_t c = bits(machInst, 8);
303 const uint32_t a = bits(machInst, 23, 21);
304 const uint32_t b = bits(machInst, 6, 5);
305 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
306 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
307 return new Unknown(machInst);
308 }
309 if (l == 0 && c == 0) {
310 if (a == 0) {
311 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
312 bits(machInst, 7);
313 const IntRegIndex rt =
314 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
315 if (bits(machInst, 20) == 1) {
316 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
317 } else {
318 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
319 }
320 } else if (a == 0x7) {
321 const IntRegIndex rt =
322 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
323 uint32_t specReg = bits(machInst, 19, 16);
324 switch (specReg) {
325 case 0:
326 specReg = MISCREG_FPSID;
327 break;
328 case 1:
329 specReg = MISCREG_FPSCR;
330 break;
331 case 8:
332 specReg = MISCREG_FPEXC;
333 break;
334 default:
335 return new Unknown(machInst);
336 }
337 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
338 }
339 } else if (l == 0 && c == 1) {
340 if (bits(a, 2) == 0) {
341 uint32_t vd = (bits(machInst, 7) << 5) |
342 (bits(machInst, 19, 16) << 1);
343 uint32_t index, size;
344 const IntRegIndex rt =
345 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
346 if (bits(machInst, 22) == 1) {
347 size = 8;
348 index = (bits(machInst, 21) << 2) |
349 bits(machInst, 6, 5);
350 } else if (bits(machInst, 5) == 1) {
351 size = 16;
352 index = (bits(machInst, 21) << 1) |
353 bits(machInst, 6);
354 } else if (bits(machInst, 6) == 0) {
355 size = 32;
356 index = bits(machInst, 21);
357 } else {
358 return new Unknown(machInst);
359 }
360 if (index >= (32 / size)) {
361 index -= (32 / size);
362 vd++;
363 }
364 switch (size) {
365 case 8:
366 return new VmovCoreRegB(machInst, (IntRegIndex)vd,
367 rt, index);
368 case 16:
369 return new VmovCoreRegH(machInst, (IntRegIndex)vd,
370 rt, index);
371 case 32:
372 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
373 }
374 } else if (bits(b, 1) == 0) {
375 // A8-594
376 return new WarnUnimplemented("vdup", machInst);
377 }
378 } else if (l == 1 && c == 0) {
379 if (a == 0) {
380 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
381 bits(machInst, 7);
382 const IntRegIndex rt =
383 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
384 if (bits(machInst, 20) == 1) {
385 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
386 } else {
387 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
388 }
389 } else if (a == 7) {
390 const IntRegIndex rt =
391 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
392 uint32_t specReg = bits(machInst, 19, 16);
393 switch (specReg) {
394 case 0:
395 specReg = MISCREG_FPSID;
396 break;
397 case 1:
398 specReg = MISCREG_FPSCR;
399 break;
400 case 6:
401 specReg = MISCREG_MVFR1;
402 break;
403 case 7:
404 specReg = MISCREG_MVFR0;
405 break;
406 case 8:
407 specReg = MISCREG_FPEXC;
408 break;
409 default:
410 return new Unknown(machInst);
411 }
412 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
413 }
414 } else {
415 uint32_t vd = (bits(machInst, 7) << 5) |
416 (bits(machInst, 19, 16) << 1);
417 uint32_t index, size;
418 const IntRegIndex rt =
419 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
420 const bool u = (bits(machInst, 23) == 1);
421 if (bits(machInst, 22) == 1) {
422 size = 8;
423 index = (bits(machInst, 21) << 2) |
424 bits(machInst, 6, 5);
425 } else if (bits(machInst, 5) == 1) {
426 size = 16;
427 index = (bits(machInst, 21) << 1) |
428 bits(machInst, 6);
429 } else if (bits(machInst, 6) == 0 && !u) {
430 size = 32;
431 index = bits(machInst, 21);
432 } else {
433 return new Unknown(machInst);
434 }
435 if (index >= (32 / size)) {
436 index -= (32 / size);
437 vd++;
438 }
439 switch (size) {
440 case 8:
441 if (u) {
442 return new VmovRegCoreUB(machInst, rt,
443 (IntRegIndex)vd, index);
444 } else {
445 return new VmovRegCoreSB(machInst, rt,
446 (IntRegIndex)vd, index);
447 }
448 case 16:
449 if (u) {
450 return new VmovRegCoreUH(machInst, rt,
451 (IntRegIndex)vd, index);
452 } else {
453 return new VmovRegCoreSH(machInst, rt,
454 (IntRegIndex)vd, index);
455 }
456 case 32:
457 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
458 }
459 }
460 return new Unknown(machInst);
461 }
462 '''
463}};
464
465def format ShortFpTransfer() {{
466 decode_block = '''
467 return decodeShortFpTransfer(machInst);
468 '''
469}};
470
471let {{
472 header_output = '''
473 StaticInstPtr
474 decodeVfpData(ExtMachInst machInst);
475 '''
476 decoder_output = '''
477 StaticInstPtr
478 decodeVfpData(ExtMachInst machInst)
479 {
480 const uint32_t opc1 = bits(machInst, 23, 20);
481 const uint32_t opc2 = bits(machInst, 19, 16);
482 const uint32_t opc3 = bits(machInst, 7, 6);
483 //const uint32_t opc4 = bits(machInst, 3, 0);
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48def template FPAExecute {{
49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
50 {
51 Fault fault = NoFault;
52
53 %(fp_enable_check)s;
54
55 %(op_decl)s;
56 %(op_rd)s;
57
58 if (%(predicate_test)s) {
59 %(code)s;
60 if (fault == NoFault) {
61 %(op_wb)s;
62 }
63 }
64
65 return fault;
66 }
67}};
68
69def template FloatDoubleDecode {{
70 {
71 ArmStaticInst *i = NULL;
72 switch (OPCODE_19 << 1 | OPCODE_7)
73 {
74 case 0:
75 i = (ArmStaticInst *)new %(class_name)sS(machInst);
76 break;
77 case 1:
78 i = (ArmStaticInst *)new %(class_name)sD(machInst);
79 break;
80 case 2:
81 case 3:
82 default:
83 panic("Cannot decode float/double nature of the instruction");
84 }
85 return i;
86 }
87}};
88
89// Primary format for float point operate instructions:
90def format FloatOp(code, *flags) {{
91 orig_code = code
92
93 cblk = code
94 iop = InstObjParams(name, Name, 'PredOp',
95 {"code": cblk,
96 "predicate_test": predicateTest},
97 flags)
98 header_output = BasicDeclare.subst(iop)
99 decoder_output = BasicConstructor.subst(iop)
100 exec_output = FPAExecute.subst(iop)
101
102 sng_cblk = code
103 sng_iop = InstObjParams(name, Name+'S', 'PredOp',
104 {"code": sng_cblk,
105 "predicate_test": predicateTest},
106 flags)
107 header_output += BasicDeclare.subst(sng_iop)
108 decoder_output += BasicConstructor.subst(sng_iop)
109 exec_output += FPAExecute.subst(sng_iop)
110
111 dbl_code = re.sub(r'\.sf', '.df', orig_code)
112
113 dbl_cblk = dbl_code
114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
115 {"code": dbl_cblk,
116 "predicate_test": predicateTest},
117 flags)
118 header_output += BasicDeclare.subst(dbl_iop)
119 decoder_output += BasicConstructor.subst(dbl_iop)
120 exec_output += FPAExecute.subst(dbl_iop)
121
122 decode_block = FloatDoubleDecode.subst(iop)
123}};
124
125let {{
126 calcFPCcCode = '''
127 uint16_t _in, _iz, _ic, _iv;
128
129 _in = %(fReg1)s < %(fReg2)s;
130 _iz = %(fReg1)s == %(fReg2)s;
131 _ic = %(fReg1)s >= %(fReg2)s;
132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
133
134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
135 (CondCodes & 0x0FFFFFFF);
136 '''
137}};
138
139def format FloatCmp(fReg1, fReg2, *flags) {{
140 code = calcFPCcCode % vars()
141 iop = InstObjParams(name, Name, 'PredOp',
142 {"code": code,
143 "predicate_test": predicateTest},
144 flags)
145 header_output = BasicDeclare.subst(iop)
146 decoder_output = BasicConstructor.subst(iop)
147 decode_block = BasicDecode.subst(iop)
148 exec_output = FPAExecute.subst(iop)
149}};
150
151let {{
152 header_output = '''
153 StaticInstPtr
154 decodeExtensionRegLoadStore(ExtMachInst machInst);
155 '''
156 decoder_output = '''
157 StaticInstPtr
158 decodeExtensionRegLoadStore(ExtMachInst machInst)
159 {
160 const uint32_t opcode = bits(machInst, 24, 20);
161 const uint32_t offset = bits(machInst, 7, 0);
162 const bool single = (bits(machInst, 8) == 0);
163 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
164 RegIndex vd;
165 if (single) {
166 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
167 bits(machInst, 22));
168 } else {
169 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
170 (bits(machInst, 22) << 5));
171 }
172 switch (bits(opcode, 4, 3)) {
173 case 0x0:
174 if (bits(opcode, 4, 1) == 0x2 &&
175 !(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
176 !(machInst.thumb == 0 && machInst.condCode == 0xf)) {
177 if ((bits(machInst, 7, 4) & 0xd) != 1) {
178 break;
179 }
180 const IntRegIndex rt =
181 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
182 const IntRegIndex rt2 =
183 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
184 const bool op = bits(machInst, 20);
185 uint32_t vm;
186 if (single) {
187 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
188 } else {
189 vm = (bits(machInst, 3, 0) << 1) |
190 (bits(machInst, 5) << 5);
191 }
192 if (op) {
193 return new Vmov2Core2Reg(machInst, rt, rt2,
194 (IntRegIndex)vm);
195 } else {
196 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
197 rt, rt2);
198 }
199 }
200 break;
201 case 0x1:
202 switch (bits(opcode, 1, 0)) {
203 case 0x0:
204 return new VLdmStm(machInst, rn, vd, single,
205 true, false, false, offset);
206 case 0x1:
207 return new VLdmStm(machInst, rn, vd, single,
208 true, false, true, offset);
209 case 0x2:
210 return new VLdmStm(machInst, rn, vd, single,
211 true, true, false, offset);
212 case 0x3:
213 // If rn == sp, then this is called vpop.
214 return new VLdmStm(machInst, rn, vd, single,
215 true, true, true, offset);
216 }
217 case 0x2:
218 if (bits(opcode, 1, 0) == 0x2) {
219 // If rn == sp, then this is called vpush.
220 return new VLdmStm(machInst, rn, vd, single,
221 false, true, false, offset);
222 } else if (bits(opcode, 1, 0) == 0x3) {
223 return new VLdmStm(machInst, rn, vd, single,
224 false, true, true, offset);
225 }
226 // Fall through on purpose
227 case 0x3:
228 const bool up = (bits(machInst, 23) == 1);
229 const uint32_t imm = bits(machInst, 7, 0) << 2;
230 RegIndex vd;
231 if (single) {
232 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
233 (bits(machInst, 22)));
234 } else {
235 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
236 (bits(machInst, 22) << 5));
237 }
238 if (bits(opcode, 1, 0) == 0x0) {
239 if (single) {
240 if (up) {
241 return new %(vstr_us)s(machInst, vd, rn, up, imm);
242 } else {
243 return new %(vstr_s)s(machInst, vd, rn, up, imm);
244 }
245 } else {
246 if (up) {
247 return new %(vstr_ud)s(machInst, vd, vd + 1,
248 rn, up, imm);
249 } else {
250 return new %(vstr_d)s(machInst, vd, vd + 1,
251 rn, up, imm);
252 }
253 }
254 } else if (bits(opcode, 1, 0) == 0x1) {
255 if (single) {
256 if (up) {
257 return new %(vldr_us)s(machInst, vd, rn, up, imm);
258 } else {
259 return new %(vldr_s)s(machInst, vd, rn, up, imm);
260 }
261 } else {
262 if (up) {
263 return new %(vldr_ud)s(machInst, vd, vd + 1,
264 rn, up, imm);
265 } else {
266 return new %(vldr_d)s(machInst, vd, vd + 1,
267 rn, up, imm);
268 }
269 }
270 }
271 }
272 return new Unknown(machInst);
273 }
274 ''' % {
275 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
276 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
277 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
278 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False),
279 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False),
280 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False),
281 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False),
282 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False)
283 }
284}};
285
286def format ExtensionRegLoadStore() {{
287 decode_block = '''
288 return decodeExtensionRegLoadStore(machInst);
289 '''
290}};
291
292let {{
293 header_output = '''
294 StaticInstPtr
295 decodeShortFpTransfer(ExtMachInst machInst);
296 '''
297 decoder_output = '''
298 StaticInstPtr
299 decodeShortFpTransfer(ExtMachInst machInst)
300 {
301 const uint32_t l = bits(machInst, 20);
302 const uint32_t c = bits(machInst, 8);
303 const uint32_t a = bits(machInst, 23, 21);
304 const uint32_t b = bits(machInst, 6, 5);
305 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
306 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
307 return new Unknown(machInst);
308 }
309 if (l == 0 && c == 0) {
310 if (a == 0) {
311 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
312 bits(machInst, 7);
313 const IntRegIndex rt =
314 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
315 if (bits(machInst, 20) == 1) {
316 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
317 } else {
318 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
319 }
320 } else if (a == 0x7) {
321 const IntRegIndex rt =
322 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
323 uint32_t specReg = bits(machInst, 19, 16);
324 switch (specReg) {
325 case 0:
326 specReg = MISCREG_FPSID;
327 break;
328 case 1:
329 specReg = MISCREG_FPSCR;
330 break;
331 case 8:
332 specReg = MISCREG_FPEXC;
333 break;
334 default:
335 return new Unknown(machInst);
336 }
337 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
338 }
339 } else if (l == 0 && c == 1) {
340 if (bits(a, 2) == 0) {
341 uint32_t vd = (bits(machInst, 7) << 5) |
342 (bits(machInst, 19, 16) << 1);
343 uint32_t index, size;
344 const IntRegIndex rt =
345 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
346 if (bits(machInst, 22) == 1) {
347 size = 8;
348 index = (bits(machInst, 21) << 2) |
349 bits(machInst, 6, 5);
350 } else if (bits(machInst, 5) == 1) {
351 size = 16;
352 index = (bits(machInst, 21) << 1) |
353 bits(machInst, 6);
354 } else if (bits(machInst, 6) == 0) {
355 size = 32;
356 index = bits(machInst, 21);
357 } else {
358 return new Unknown(machInst);
359 }
360 if (index >= (32 / size)) {
361 index -= (32 / size);
362 vd++;
363 }
364 switch (size) {
365 case 8:
366 return new VmovCoreRegB(machInst, (IntRegIndex)vd,
367 rt, index);
368 case 16:
369 return new VmovCoreRegH(machInst, (IntRegIndex)vd,
370 rt, index);
371 case 32:
372 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
373 }
374 } else if (bits(b, 1) == 0) {
375 // A8-594
376 return new WarnUnimplemented("vdup", machInst);
377 }
378 } else if (l == 1 && c == 0) {
379 if (a == 0) {
380 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
381 bits(machInst, 7);
382 const IntRegIndex rt =
383 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
384 if (bits(machInst, 20) == 1) {
385 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
386 } else {
387 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
388 }
389 } else if (a == 7) {
390 const IntRegIndex rt =
391 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
392 uint32_t specReg = bits(machInst, 19, 16);
393 switch (specReg) {
394 case 0:
395 specReg = MISCREG_FPSID;
396 break;
397 case 1:
398 specReg = MISCREG_FPSCR;
399 break;
400 case 6:
401 specReg = MISCREG_MVFR1;
402 break;
403 case 7:
404 specReg = MISCREG_MVFR0;
405 break;
406 case 8:
407 specReg = MISCREG_FPEXC;
408 break;
409 default:
410 return new Unknown(machInst);
411 }
412 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
413 }
414 } else {
415 uint32_t vd = (bits(machInst, 7) << 5) |
416 (bits(machInst, 19, 16) << 1);
417 uint32_t index, size;
418 const IntRegIndex rt =
419 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
420 const bool u = (bits(machInst, 23) == 1);
421 if (bits(machInst, 22) == 1) {
422 size = 8;
423 index = (bits(machInst, 21) << 2) |
424 bits(machInst, 6, 5);
425 } else if (bits(machInst, 5) == 1) {
426 size = 16;
427 index = (bits(machInst, 21) << 1) |
428 bits(machInst, 6);
429 } else if (bits(machInst, 6) == 0 && !u) {
430 size = 32;
431 index = bits(machInst, 21);
432 } else {
433 return new Unknown(machInst);
434 }
435 if (index >= (32 / size)) {
436 index -= (32 / size);
437 vd++;
438 }
439 switch (size) {
440 case 8:
441 if (u) {
442 return new VmovRegCoreUB(machInst, rt,
443 (IntRegIndex)vd, index);
444 } else {
445 return new VmovRegCoreSB(machInst, rt,
446 (IntRegIndex)vd, index);
447 }
448 case 16:
449 if (u) {
450 return new VmovRegCoreUH(machInst, rt,
451 (IntRegIndex)vd, index);
452 } else {
453 return new VmovRegCoreSH(machInst, rt,
454 (IntRegIndex)vd, index);
455 }
456 case 32:
457 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
458 }
459 }
460 return new Unknown(machInst);
461 }
462 '''
463}};
464
465def format ShortFpTransfer() {{
466 decode_block = '''
467 return decodeShortFpTransfer(machInst);
468 '''
469}};
470
471let {{
472 header_output = '''
473 StaticInstPtr
474 decodeVfpData(ExtMachInst machInst);
475 '''
476 decoder_output = '''
477 StaticInstPtr
478 decodeVfpData(ExtMachInst machInst)
479 {
480 const uint32_t opc1 = bits(machInst, 23, 20);
481 const uint32_t opc2 = bits(machInst, 19, 16);
482 const uint32_t opc3 = bits(machInst, 7, 6);
483 //const uint32_t opc4 = bits(machInst, 3, 0);
|
| 484 const bool single = (bits(machInst, 8) == 0);
485 IntRegIndex vd;
486 IntRegIndex vm;
487 IntRegIndex vn;
488 if (single) {
489 vd = (IntRegIndex)(bits(machInst, 22) |
490 (bits(machInst, 15, 12) << 1));
491 vm = (IntRegIndex)(bits(machInst, 5) |
492 (bits(machInst, 3, 0) << 1));
493 vn = (IntRegIndex)(bits(machInst, 7) |
494 (bits(machInst, 19, 16) << 1));
495 } else {
496 vd = (IntRegIndex)((bits(machInst, 22) << 5) |
497 (bits(machInst, 15, 12) << 1));
498 vm = (IntRegIndex)((bits(machInst, 5) << 5) |
499 (bits(machInst, 3, 0) << 1));
500 vn = (IntRegIndex)((bits(machInst, 7) << 5) |
501 (bits(machInst, 19, 16) << 1));
502 }
|
484 switch (opc1 & 0xb /* 1011 */) {
485 case 0x0:
486 if (bits(machInst, 6) == 0) {
| 503 switch (opc1 & 0xb /* 1011 */) {
504 case 0x0:
505 if (bits(machInst, 6) == 0) {
|
487 uint32_t vd;
488 uint32_t vm;
489 uint32_t vn;
490 if (bits(machInst, 8) == 0) {
491 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
492 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
493 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
494 return new VmlaS(machInst, (IntRegIndex)vd,
495 (IntRegIndex)vn, (IntRegIndex)vm);
| 506 if (single) {
507 return new VmlaS(machInst, vd, vn, vm);
|
496 } else {
| 508 } else {
|
497 vd = (bits(machInst, 22) << 5) |
498 (bits(machInst, 15, 12) << 1);
499 vm = (bits(machInst, 5) << 5) |
500 (bits(machInst, 3, 0) << 1);
501 vn = (bits(machInst, 7) << 5) |
502 (bits(machInst, 19, 16) << 1);
503 return new VmlaD(machInst, (IntRegIndex)vd,
504 (IntRegIndex)vn, (IntRegIndex)vm);
| 509 return new VmlaD(machInst, vd, vn, vm);
|
505 }
506 } else {
| 510 }
511 } else {
|
507 uint32_t vd;
508 uint32_t vm;
509 uint32_t vn;
510 if (bits(machInst, 8) == 0) {
511 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
512 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
513 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
514 return new VmlsS(machInst, (IntRegIndex)vd,
515 (IntRegIndex)vn, (IntRegIndex)vm);
| 512 if (single) {
513 return new VmlsS(machInst, vd, vn, vm);
|
516 } else {
| 514 } else {
|
517 vd = (bits(machInst, 22) << 5) |
518 (bits(machInst, 15, 12) << 1);
519 vm = (bits(machInst, 5) << 5) |
520 (bits(machInst, 3, 0) << 1);
521 vn = (bits(machInst, 7) << 5) |
522 (bits(machInst, 19, 16) << 1);
523 return new VmlsD(machInst, (IntRegIndex)vd,
524 (IntRegIndex)vn, (IntRegIndex)vm);
| 515 return new VmlsD(machInst, vd, vn, vm);
|
525 }
526 }
527 case 0x1:
528 if (bits(machInst, 6) == 1) {
| 516 }
517 }
518 case 0x1:
519 if (bits(machInst, 6) == 1) {
|
529 uint32_t vd;
530 uint32_t vm;
531 uint32_t vn;
532 if (bits(machInst, 8) == 0) {
533 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
534 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
535 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
536 return new VnmlaS(machInst, (IntRegIndex)vd,
537 (IntRegIndex)vn, (IntRegIndex)vm);
| 520 if (single) {
521 return new VnmlaS(machInst, vd, vn, vm);
|
538 } else {
| 522 } else {
|
539 vd = (bits(machInst, 22) << 5) |
540 (bits(machInst, 15, 12) << 1);
541 vm = (bits(machInst, 5) << 5) |
542 (bits(machInst, 3, 0) << 1);
543 vn = (bits(machInst, 7) << 5) |
544 (bits(machInst, 19, 16) << 1);
545 return new VnmlaD(machInst, (IntRegIndex)vd,
546 (IntRegIndex)vn, (IntRegIndex)vm);
| 523 return new VnmlaD(machInst, vd, vn, vm);
|
547 }
548 } else {
| 524 }
525 } else {
|
549 uint32_t vd;
550 uint32_t vm;
551 uint32_t vn;
552 if (bits(machInst, 8) == 0) {
553 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
554 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
555 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
556 return new VnmlsS(machInst, (IntRegIndex)vd,
557 (IntRegIndex)vn, (IntRegIndex)vm);
| 526 if (single) {
527 return new VnmlsS(machInst, vd, vn, vm);
|
558 } else {
| 528 } else {
|
559 vd = (bits(machInst, 22) << 5) |
560 (bits(machInst, 15, 12) << 1);
561 vm = (bits(machInst, 5) << 5) |
562 (bits(machInst, 3, 0) << 1);
563 vn = (bits(machInst, 7) << 5) |
564 (bits(machInst, 19, 16) << 1);
565 return new VnmlsD(machInst, (IntRegIndex)vd,
566 (IntRegIndex)vn, (IntRegIndex)vm);
| 529 return new VnmlsD(machInst, vd, vn, vm);
|
567 }
568 }
569 case 0x2:
570 if ((opc3 & 0x1) == 0) {
| 530 }
531 }
532 case 0x2:
533 if ((opc3 & 0x1) == 0) {
|
571 uint32_t vd;
572 uint32_t vm;
573 uint32_t vn;
574 if (bits(machInst, 8) == 0) {
575 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
576 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
577 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
578 return new VmulS(machInst, (IntRegIndex)vd,
579 (IntRegIndex)vn, (IntRegIndex)vm);
| 534 if (single) {
535 return new VmulS(machInst, vd, vn, vm);
|
580 } else {
| 536 } else {
|
581 vd = (bits(machInst, 22) << 5) |
582 (bits(machInst, 15, 12) << 1);
583 vm = (bits(machInst, 5) << 5) |
584 (bits(machInst, 3, 0) << 1);
585 vn = (bits(machInst, 7) << 5) |
586 (bits(machInst, 19, 16) << 1);
587 return new VmulD(machInst, (IntRegIndex)vd,
588 (IntRegIndex)vn, (IntRegIndex)vm);
| 537 return new VmulD(machInst, vd, vn, vm);
|
589 }
590 } else {
| 538 }
539 } else {
|
591 uint32_t vd;
592 uint32_t vm;
593 uint32_t vn;
594 if (bits(machInst, 8) == 0) {
595 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
596 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
597 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
598 return new VnmulS(machInst, (IntRegIndex)vd,
599 (IntRegIndex)vn, (IntRegIndex)vm);
| 540 if (single) {
541 return new VnmulS(machInst, vd, vn, vm);
|
600 } else {
| 542 } else {
|
601 vd = (bits(machInst, 22) << 5) |
602 (bits(machInst, 15, 12) << 1);
603 vm = (bits(machInst, 5) << 5) |
604 (bits(machInst, 3, 0) << 1);
605 vn = (bits(machInst, 7) << 5) |
606 (bits(machInst, 19, 16) << 1);
607 return new VnmulD(machInst, (IntRegIndex)vd,
608 (IntRegIndex)vn, (IntRegIndex)vm);
| 543 return new VnmulD(machInst, vd, vn, vm);
|
609 }
610 }
611 case 0x3:
612 if ((opc3 & 0x1) == 0) {
| 544 }
545 }
546 case 0x3:
547 if ((opc3 & 0x1) == 0) {
|
613 uint32_t vd;
614 uint32_t vm;
615 uint32_t vn;
616 if (bits(machInst, 8) == 0) {
617 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
618 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
619 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
620 return new VaddS(machInst, (IntRegIndex)vd,
621 (IntRegIndex)vn, (IntRegIndex)vm);
| 548 if (single) {
549 return new VaddS(machInst, vd, vn, vm);
|
622 } else {
| 550 } else {
|
623 vd = (bits(machInst, 22) << 5) |
624 (bits(machInst, 15, 12) << 1);
625 vm = (bits(machInst, 5) << 5) |
626 (bits(machInst, 3, 0) << 1);
627 vn = (bits(machInst, 7) << 5) |
628 (bits(machInst, 19, 16) << 1);
629 return new VaddD(machInst, (IntRegIndex)vd,
630 (IntRegIndex)vn, (IntRegIndex)vm);
| 551 return new VaddD(machInst, vd, vn, vm);
|
631 }
632 } else {
| 552 }
553 } else {
|
633 uint32_t vd;
634 uint32_t vm;
635 uint32_t vn;
636 if (bits(machInst, 8) == 0) {
637 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
638 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
639 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
640 return new VsubS(machInst, (IntRegIndex)vd,
641 (IntRegIndex)vn, (IntRegIndex)vm);
| 554 if (single) {
555 return new VsubS(machInst, vd, vn, vm);
|
642 } else {
| 556 } else {
|
643 vd = (bits(machInst, 22) << 5) |
644 (bits(machInst, 15, 12) << 1);
645 vm = (bits(machInst, 5) << 5) |
646 (bits(machInst, 3, 0) << 1);
647 vn = (bits(machInst, 7) << 5) |
648 (bits(machInst, 19, 16) << 1);
649 return new VsubD(machInst, (IntRegIndex)vd,
650 (IntRegIndex)vn, (IntRegIndex)vm);
| 557 return new VsubD(machInst, vd, vn, vm);
|
651 }
652 }
653 case 0x8:
654 if ((opc3 & 0x1) == 0) {
| 558 }
559 }
560 case 0x8:
561 if ((opc3 & 0x1) == 0) {
|
655 uint32_t vd;
656 uint32_t vm;
657 uint32_t vn;
658 if (bits(machInst, 8) == 0) {
659 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
660 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
661 vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
662 return new VdivS(machInst, (IntRegIndex)vd,
663 (IntRegIndex)vn, (IntRegIndex)vm);
| 562 if (single) {
563 return new VdivS(machInst, vd, vn, vm);
|
664 } else {
| 564 } else {
|
665 vd = (bits(machInst, 22) << 5) |
666 (bits(machInst, 15, 12) << 1);
667 vm = (bits(machInst, 5) << 5) |
668 (bits(machInst, 3, 0) << 1);
669 vn = (bits(machInst, 7) << 5) |
670 (bits(machInst, 19, 16) << 1);
671 return new VdivD(machInst, (IntRegIndex)vd,
672 (IntRegIndex)vn, (IntRegIndex)vm);
| 565 return new VdivD(machInst, vd, vn, vm);
|
673 }
674 }
675 break;
676 case 0xb:
677 if ((opc3 & 0x1) == 0) {
| 566 }
567 }
568 break;
569 case 0xb:
570 if ((opc3 & 0x1) == 0) {
|
678 uint32_t vd;
| |
679 const uint32_t baseImm =
680 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
| 571 const uint32_t baseImm =
572 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
|
681 if (bits(machInst, 8) == 0) {
682 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
| 573 if (single) {
|
683 uint32_t imm = vfp_modified_imm(baseImm, false);
| 574 uint32_t imm = vfp_modified_imm(baseImm, false);
|
684 return new VmovImmS(machInst, (IntRegIndex)vd, imm);
| 575 return new VmovImmS(machInst, vd, imm);
|
685 } else {
| 576 } else {
|
686 vd = (bits(machInst, 22) << 5) |
687 (bits(machInst, 15, 12) << 1);
| |
688 uint64_t imm = vfp_modified_imm(baseImm, true);
| 577 uint64_t imm = vfp_modified_imm(baseImm, true);
|
689 return new VmovImmD(machInst, (IntRegIndex)vd, imm);
| 578 return new VmovImmD(machInst, vd, imm);
|
690 }
691 }
692 switch (opc2) {
693 case 0x0:
694 if (opc3 == 1) {
| 579 }
580 }
581 switch (opc2) {
582 case 0x0:
583 if (opc3 == 1) {
|
695 uint32_t vd;
696 uint32_t vm;
697 if (bits(machInst, 8) == 0) {
698 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
699 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
700 return new VmovRegS(machInst,
701 (IntRegIndex)vd, (IntRegIndex)vm);
| 584 if (single) {
585 return new VmovRegS(machInst, vd, vm);
|
702 } else {
| 586 } else {
|
703 vd = (bits(machInst, 22) << 5) |
704 (bits(machInst, 15, 12) << 1);
705 vm = (bits(machInst, 5) << 5) |
706 (bits(machInst, 3, 0) << 1);
707 return new VmovRegD(machInst,
708 (IntRegIndex)vd, (IntRegIndex)vm);
| 587 return new VmovRegD(machInst, vd, vm);
|
709 }
710 } else {
| 588 }
589 } else {
|
711 uint32_t vd;
712 uint32_t vm;
713 if (bits(machInst, 8) == 0) {
714 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
715 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
716 return new VabsS(machInst,
717 (IntRegIndex)vd, (IntRegIndex)vm);
| 590 if (single) {
591 return new VabsS(machInst, vd, vm);
|
718 } else {
| 592 } else {
|
719 vd = (bits(machInst, 22) << 5) |
720 (bits(machInst, 15, 12) << 1);
721 vm = (bits(machInst, 5) << 5) |
722 (bits(machInst, 3, 0) << 1);
723 return new VabsD(machInst,
724 (IntRegIndex)vd, (IntRegIndex)vm);
| 593 return new VabsD(machInst, vd, vm);
|
725 }
726 }
727 case 0x1:
728 if (opc3 == 1) {
| 594 }
595 }
596 case 0x1:
597 if (opc3 == 1) {
|
729 uint32_t vd;
730 uint32_t vm;
731 if (bits(machInst, 8) == 0) {
732 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
733 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
734 return new VnegS(machInst,
735 (IntRegIndex)vd, (IntRegIndex)vm);
| 598 if (single) {
599 return new VnegS(machInst, vd, vm);
|
736 } else {
| 600 } else {
|
737 vd = (bits(machInst, 22) << 5) |
738 (bits(machInst, 15, 12) << 1);
739 vm = (bits(machInst, 5) << 5) |
740 (bits(machInst, 3, 0) << 1);
741 return new VnegD(machInst,
742 (IntRegIndex)vd, (IntRegIndex)vm);
| 601 return new VnegD(machInst, vd, vm);
|
743 }
744 } else {
| 602 }
603 } else {
|
745 uint32_t vd;
746 uint32_t vm;
747 if (bits(machInst, 8) == 0) {
748 vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
749 vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
750 return new VsqrtS(machInst,
751 (IntRegIndex)vd, (IntRegIndex)vm);
| 604 if (single) {
605 return new VsqrtS(machInst, vd, vm);
|
752 } else {
| 606 } else {
|
753 vd = (bits(machInst, 22) << 5) |
754 (bits(machInst, 15, 12) << 1);
755 vm = (bits(machInst, 5) << 5) |
756 (bits(machInst, 3, 0) << 1);
757 return new VsqrtD(machInst,
758 (IntRegIndex)vd, (IntRegIndex)vm);
| 607 return new VsqrtD(machInst, vd, vm);
|
759 }
760 }
761 case 0x2:
762 case 0x3:
763 // Between half and single precision.
764 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
765 case 0x4:
766 case 0x5:
767 return new WarnUnimplemented("vcmp, vcmpe", machInst);
768 case 0x7:
769 if (opc3 == 0x3) {
770 // Between double and single precision.
771 return new WarnUnimplemented("vcvt", machInst);
772 }
773 break;
774 case 0x8:
775 // Between FP and int.
776 return new WarnUnimplemented("vcvt, vcvtr", machInst);
777 case 0xa:
778 case 0xb:
779 // Between FP and fixed point.
780 return new WarnUnimplemented("vcvt", machInst);
781 case 0xc:
782 case 0xd:
783 // Between FP and int.
784 return new WarnUnimplemented("vcvt, vcvtr", machInst);
785 case 0xe:
786 case 0xf:
787 // Between FP and fixed point.
788 return new WarnUnimplemented("vcvt", machInst);
789 }
790 break;
791 }
792 return new Unknown(machInst);
793 }
794 '''
795}};
796
797def format VfpData() {{
798 decode_block = '''
799 return decodeVfpData(machInst);
800 '''
801}};
| 608 }
609 }
610 case 0x2:
611 case 0x3:
612 // Between half and single precision.
613 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
614 case 0x4:
615 case 0x5:
616 return new WarnUnimplemented("vcmp, vcmpe", machInst);
617 case 0x7:
618 if (opc3 == 0x3) {
619 // Between double and single precision.
620 return new WarnUnimplemented("vcvt", machInst);
621 }
622 break;
623 case 0x8:
624 // Between FP and int.
625 return new WarnUnimplemented("vcvt, vcvtr", machInst);
626 case 0xa:
627 case 0xb:
628 // Between FP and fixed point.
629 return new WarnUnimplemented("vcvt", machInst);
630 case 0xc:
631 case 0xd:
632 // Between FP and int.
633 return new WarnUnimplemented("vcvt, vcvtr", machInst);
634 case 0xe:
635 case 0xf:
636 // Between FP and fixed point.
637 return new WarnUnimplemented("vcvt", machInst);
638 }
639 break;
640 }
641 return new Unknown(machInst);
642 }
643 '''
644}};
645
646def format VfpData() {{
647 decode_block = '''
648 return decodeVfpData(machInst);
649 '''
650}};
|