1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48def template FPAExecute {{
49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
50 {
51 Fault fault = NoFault;
52
53 %(fp_enable_check)s;
54
55 %(op_decl)s;
56 %(op_rd)s;
57
58 if (%(predicate_test)s) {
59 %(code)s;
60 if (fault == NoFault) {
61 %(op_wb)s;
62 }
63 }
64
65 return fault;
66 }
67}};
68
69def template FloatDoubleDecode {{
70 {
71 ArmStaticInst *i = NULL;
72 switch (OPCODE_19 << 1 | OPCODE_7)
73 {
74 case 0:
75 i = (ArmStaticInst *)new %(class_name)sS(machInst);
76 break;
77 case 1:
78 i = (ArmStaticInst *)new %(class_name)sD(machInst);
79 break;
80 case 2:
81 case 3:
82 default:
83 panic("Cannot decode float/double nature of the instruction");
84 }
85 return i;
86 }
87}};
88
89// Primary format for float point operate instructions:
90def format FloatOp(code, *flags) {{
91 orig_code = code
92
93 cblk = code
94 iop = InstObjParams(name, Name, 'PredOp',
95 {"code": cblk,
96 "predicate_test": predicateTest},
97 flags)
98 header_output = BasicDeclare.subst(iop)
99 decoder_output = BasicConstructor.subst(iop)
100 exec_output = FPAExecute.subst(iop)
101
102 sng_cblk = code
103 sng_iop = InstObjParams(name, Name+'S', 'PredOp',
104 {"code": sng_cblk,
105 "predicate_test": predicateTest},
106 flags)
107 header_output += BasicDeclare.subst(sng_iop)
108 decoder_output += BasicConstructor.subst(sng_iop)
109 exec_output += FPAExecute.subst(sng_iop)
110
111 dbl_code = re.sub(r'\.sf', '.df', orig_code)
112
113 dbl_cblk = dbl_code
114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
115 {"code": dbl_cblk,
116 "predicate_test": predicateTest},
117 flags)
118 header_output += BasicDeclare.subst(dbl_iop)
119 decoder_output += BasicConstructor.subst(dbl_iop)
120 exec_output += FPAExecute.subst(dbl_iop)
121
122 decode_block = FloatDoubleDecode.subst(iop)
123}};
124
125let {{
126 calcFPCcCode = '''
127 uint16_t _in, _iz, _ic, _iv;
128
129 _in = %(fReg1)s < %(fReg2)s;
130 _iz = %(fReg1)s == %(fReg2)s;
131 _ic = %(fReg1)s >= %(fReg2)s;
132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
133
134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
135 (CondCodes & 0x0FFFFFFF);
136 '''
137}};
138
139def format FloatCmp(fReg1, fReg2, *flags) {{
140 code = calcFPCcCode % vars()
141 iop = InstObjParams(name, Name, 'PredOp',
142 {"code": code,
143 "predicate_test": predicateTest},
144 flags)
145 header_output = BasicDeclare.subst(iop)
146 decoder_output = BasicConstructor.subst(iop)
147 decode_block = BasicDecode.subst(iop)
148 exec_output = FPAExecute.subst(iop)
149}};
150
151def format ExtensionRegLoadStore() {{
152 decode_block = '''
153 {
154 const uint32_t opcode = bits(machInst, 24, 20);
155 const uint32_t offset = bits(machInst, 7, 0);
156 const bool single = bits(machInst, 22);
157 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
158 RegIndex vd;
159 if (single) {
160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
161 bits(machInst, 22));
162 } else {
163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
164 (bits(machInst, 22) << 5));
165 }
166 switch (bits(opcode, 4, 3)) {
167 case 0x0:
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Floating Point operate instructions
46//
47
48def template FPAExecute {{
49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
50 {
51 Fault fault = NoFault;
52
53 %(fp_enable_check)s;
54
55 %(op_decl)s;
56 %(op_rd)s;
57
58 if (%(predicate_test)s) {
59 %(code)s;
60 if (fault == NoFault) {
61 %(op_wb)s;
62 }
63 }
64
65 return fault;
66 }
67}};
68
69def template FloatDoubleDecode {{
70 {
71 ArmStaticInst *i = NULL;
72 switch (OPCODE_19 << 1 | OPCODE_7)
73 {
74 case 0:
75 i = (ArmStaticInst *)new %(class_name)sS(machInst);
76 break;
77 case 1:
78 i = (ArmStaticInst *)new %(class_name)sD(machInst);
79 break;
80 case 2:
81 case 3:
82 default:
83 panic("Cannot decode float/double nature of the instruction");
84 }
85 return i;
86 }
87}};
88
89// Primary format for float point operate instructions:
90def format FloatOp(code, *flags) {{
91 orig_code = code
92
93 cblk = code
94 iop = InstObjParams(name, Name, 'PredOp',
95 {"code": cblk,
96 "predicate_test": predicateTest},
97 flags)
98 header_output = BasicDeclare.subst(iop)
99 decoder_output = BasicConstructor.subst(iop)
100 exec_output = FPAExecute.subst(iop)
101
102 sng_cblk = code
103 sng_iop = InstObjParams(name, Name+'S', 'PredOp',
104 {"code": sng_cblk,
105 "predicate_test": predicateTest},
106 flags)
107 header_output += BasicDeclare.subst(sng_iop)
108 decoder_output += BasicConstructor.subst(sng_iop)
109 exec_output += FPAExecute.subst(sng_iop)
110
111 dbl_code = re.sub(r'\.sf', '.df', orig_code)
112
113 dbl_cblk = dbl_code
114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
115 {"code": dbl_cblk,
116 "predicate_test": predicateTest},
117 flags)
118 header_output += BasicDeclare.subst(dbl_iop)
119 decoder_output += BasicConstructor.subst(dbl_iop)
120 exec_output += FPAExecute.subst(dbl_iop)
121
122 decode_block = FloatDoubleDecode.subst(iop)
123}};
124
125let {{
126 calcFPCcCode = '''
127 uint16_t _in, _iz, _ic, _iv;
128
129 _in = %(fReg1)s < %(fReg2)s;
130 _iz = %(fReg1)s == %(fReg2)s;
131 _ic = %(fReg1)s >= %(fReg2)s;
132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
133
134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
135 (CondCodes & 0x0FFFFFFF);
136 '''
137}};
138
139def format FloatCmp(fReg1, fReg2, *flags) {{
140 code = calcFPCcCode % vars()
141 iop = InstObjParams(name, Name, 'PredOp',
142 {"code": code,
143 "predicate_test": predicateTest},
144 flags)
145 header_output = BasicDeclare.subst(iop)
146 decoder_output = BasicConstructor.subst(iop)
147 decode_block = BasicDecode.subst(iop)
148 exec_output = FPAExecute.subst(iop)
149}};
150
151def format ExtensionRegLoadStore() {{
152 decode_block = '''
153 {
154 const uint32_t opcode = bits(machInst, 24, 20);
155 const uint32_t offset = bits(machInst, 7, 0);
156 const bool single = bits(machInst, 22);
157 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
158 RegIndex vd;
159 if (single) {
160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
161 bits(machInst, 22));
162 } else {
163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
164 (bits(machInst, 22) << 5));
165 }
166 switch (bits(opcode, 4, 3)) {
167 case 0x0:
|
168 if (bits(opcode, 4, 1) == 0x2) {
169 return new WarnUnimplemented("core-to-extension-transfer",
170 machInst);
| 168 if (bits(opcode, 4, 1) == 0x2 &&
169 !(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
170 !(machInst.thumb == 0 && machInst.condCode == 0xf)) {
171 if ((bits(machInst, 7, 4) & 0xd) != 1) {
172 break;
173 }
174 const IntRegIndex rt =
175 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
176 const IntRegIndex rt2 =
177 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
178 const bool op = bits(machInst, 20);
179 uint32_t vm;
180 if (bits(machInst, 8) == 0) {
181 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
182 } else {
183 vm = (bits(machInst, 3, 0) << 1) |
184 (bits(machInst, 5) << 5);
185 }
186 if (op) {
187 return new Vmov2Core2Reg(machInst, rt, rt2,
188 (IntRegIndex)vm);
189 } else {
190 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
191 rt, rt2);
192 }
|
171 }
172 break;
173 case 0x1:
174 switch (bits(opcode, 1, 0)) {
175 case 0x0:
176 return new VLdmStm(machInst, rn, vd, single,
177 true, false, false, offset);
178 case 0x1:
179 return new VLdmStm(machInst, rn, vd, single,
180 true, false, true, offset);
181 case 0x2:
182 return new VLdmStm(machInst, rn, vd, single,
183 true, true, false, offset);
184 case 0x3:
185 // If rn == sp, then this is called vpop.
186 return new VLdmStm(machInst, rn, vd, single,
187 true, true, true, offset);
188 }
189 case 0x2:
190 if (bits(opcode, 1, 0) == 0x2) {
191 // If rn == sp, then this is called vpush.
192 return new VLdmStm(machInst, rn, vd, single,
193 false, true, false, offset);
194 } else if (bits(opcode, 1, 0) == 0x3) {
195 return new VLdmStm(machInst, rn, vd, single,
196 false, true, true, offset);
197 }
198 // Fall through on purpose
199 case 0x3:
200 if (bits(opcode, 1, 0) == 0x0) {
201 return new WarnUnimplemented("vstr", machInst);
202 } else if (bits(opcode, 1, 0) == 0x1) {
203 return new WarnUnimplemented("vldr", machInst);
204 }
205 }
206 return new Unknown(machInst);
207 }
208 '''
209}};
210
211def format ShortFpTransfer() {{
212 decode_block = '''
213 {
214 const uint32_t l = bits(machInst, 20);
215 const uint32_t c = bits(machInst, 8);
216 const uint32_t a = bits(machInst, 23, 21);
217 const uint32_t b = bits(machInst, 6, 5);
218 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
219 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
220 return new Unknown(machInst);
221 }
222 if (l == 0 && c == 0) {
223 if (a == 0) {
| 193 }
194 break;
195 case 0x1:
196 switch (bits(opcode, 1, 0)) {
197 case 0x0:
198 return new VLdmStm(machInst, rn, vd, single,
199 true, false, false, offset);
200 case 0x1:
201 return new VLdmStm(machInst, rn, vd, single,
202 true, false, true, offset);
203 case 0x2:
204 return new VLdmStm(machInst, rn, vd, single,
205 true, true, false, offset);
206 case 0x3:
207 // If rn == sp, then this is called vpop.
208 return new VLdmStm(machInst, rn, vd, single,
209 true, true, true, offset);
210 }
211 case 0x2:
212 if (bits(opcode, 1, 0) == 0x2) {
213 // If rn == sp, then this is called vpush.
214 return new VLdmStm(machInst, rn, vd, single,
215 false, true, false, offset);
216 } else if (bits(opcode, 1, 0) == 0x3) {
217 return new VLdmStm(machInst, rn, vd, single,
218 false, true, true, offset);
219 }
220 // Fall through on purpose
221 case 0x3:
222 if (bits(opcode, 1, 0) == 0x0) {
223 return new WarnUnimplemented("vstr", machInst);
224 } else if (bits(opcode, 1, 0) == 0x1) {
225 return new WarnUnimplemented("vldr", machInst);
226 }
227 }
228 return new Unknown(machInst);
229 }
230 '''
231}};
232
233def format ShortFpTransfer() {{
234 decode_block = '''
235 {
236 const uint32_t l = bits(machInst, 20);
237 const uint32_t c = bits(machInst, 8);
238 const uint32_t a = bits(machInst, 23, 21);
239 const uint32_t b = bits(machInst, 6, 5);
240 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
241 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
242 return new Unknown(machInst);
243 }
244 if (l == 0 && c == 0) {
245 if (a == 0) {
|
224 // A8-648
225 return new WarnUnimplemented("vmov", machInst);
| 246 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
247 bits(machInst, 7);
248 const IntRegIndex rt =
249 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
250 if (bits(machInst, 20) == 1) {
251 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
252 } else {
253 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
254 }
|
226 } else if (a == 0x7) {
227 const IntRegIndex rt =
228 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
229 uint32_t specReg = bits(machInst, 19, 16);
230 switch (specReg) {
231 case 0:
232 specReg = MISCREG_FPSID;
233 break;
234 case 1:
235 specReg = MISCREG_FPSCR;
236 break;
237 case 8:
238 specReg = MISCREG_FPEXC;
239 break;
240 default:
241 return new Unknown(machInst);
242 }
243 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
244 }
245 } else if (l == 0 && c == 1) {
246 if (bits(a, 2) == 0) {
| 255 } else if (a == 0x7) {
256 const IntRegIndex rt =
257 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
258 uint32_t specReg = bits(machInst, 19, 16);
259 switch (specReg) {
260 case 0:
261 specReg = MISCREG_FPSID;
262 break;
263 case 1:
264 specReg = MISCREG_FPSCR;
265 break;
266 case 8:
267 specReg = MISCREG_FPEXC;
268 break;
269 default:
270 return new Unknown(machInst);
271 }
272 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
273 }
274 } else if (l == 0 && c == 1) {
275 if (bits(a, 2) == 0) {
|
247 // A8-644
248 return new WarnUnimplemented("vmov", machInst);
| 276 uint32_t vd = (bits(machInst, 7) << 5) |
277 (bits(machInst, 19, 16) << 1);
278 uint32_t index, size;
279 const IntRegIndex rt =
280 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
281 if (bits(machInst, 22) == 1) {
282 size = 8;
283 index = (bits(machInst, 21) << 2) |
284 bits(machInst, 6, 5);
285 } else if (bits(machInst, 5) == 1) {
286 size = 16;
287 index = (bits(machInst, 21) << 1) |
288 bits(machInst, 6);
289 } else if (bits(machInst, 6) == 0) {
290 size = 32;
291 index = bits(machInst, 21);
292 } else {
293 return new Unknown(machInst);
294 }
295 if (index >= (32 / size)) {
296 index -= (32 / size);
297 vd++;
298 }
299 switch (size) {
300 case 8:
301 return new VmovCoreRegB(machInst, (IntRegIndex)vd,
302 rt, index);
303 case 16:
304 return new VmovCoreRegH(machInst, (IntRegIndex)vd,
305 rt, index);
306 case 32:
307 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
308 }
|
249 } else if (bits(b, 1) == 0) {
250 // A8-594
251 return new WarnUnimplemented("vdup", machInst);
252 }
253 } else if (l == 1 && c == 0) {
254 if (a == 0) {
| 309 } else if (bits(b, 1) == 0) {
310 // A8-594
311 return new WarnUnimplemented("vdup", machInst);
312 }
313 } else if (l == 1 && c == 0) {
314 if (a == 0) {
|
255 // A8-648
256 return new WarnUnimplemented("vmov", machInst);
| 315 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
316 bits(machInst, 7);
317 const IntRegIndex rt =
318 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
319 if (bits(machInst, 20) == 1) {
320 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
321 } else {
322 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
323 }
|
257 } else if (a == 7) {
258 const IntRegIndex rt =
259 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
260 uint32_t specReg = bits(machInst, 19, 16);
261 switch (specReg) {
262 case 0:
263 specReg = MISCREG_FPSID;
264 break;
265 case 1:
266 specReg = MISCREG_FPSCR;
267 break;
268 case 6:
269 specReg = MISCREG_MVFR1;
270 break;
271 case 7:
272 specReg = MISCREG_MVFR0;
273 break;
274 case 8:
275 specReg = MISCREG_FPEXC;
276 break;
277 default:
278 return new Unknown(machInst);
279 }
280 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
281 }
282 } else {
| 324 } else if (a == 7) {
325 const IntRegIndex rt =
326 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
327 uint32_t specReg = bits(machInst, 19, 16);
328 switch (specReg) {
329 case 0:
330 specReg = MISCREG_FPSID;
331 break;
332 case 1:
333 specReg = MISCREG_FPSCR;
334 break;
335 case 6:
336 specReg = MISCREG_MVFR1;
337 break;
338 case 7:
339 specReg = MISCREG_MVFR0;
340 break;
341 case 8:
342 specReg = MISCREG_FPEXC;
343 break;
344 default:
345 return new Unknown(machInst);
346 }
347 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
348 }
349 } else {
|
283 // A8-646
284 return new WarnUnimplemented("vmov", machInst);
| 350 uint32_t vd = (bits(machInst, 7) << 5) |
351 (bits(machInst, 19, 16) << 1);
352 uint32_t index, size;
353 const IntRegIndex rt =
354 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
355 const bool u = (bits(machInst, 23) == 1);
356 if (bits(machInst, 22) == 1) {
357 size = 8;
358 index = (bits(machInst, 21) << 2) |
359 bits(machInst, 6, 5);
360 } else if (bits(machInst, 5) == 1) {
361 size = 16;
362 index = (bits(machInst, 21) << 1) |
363 bits(machInst, 6);
364 } else if (bits(machInst, 6) == 0 && !u) {
365 size = 32;
366 index = bits(machInst, 21);
367 } else {
368 return new Unknown(machInst);
369 }
370 if (index >= (32 / size)) {
371 index -= (32 / size);
372 vd++;
373 }
374 switch (size) {
375 case 8:
376 if (u) {
377 return new VmovRegCoreUB(machInst, rt,
378 (IntRegIndex)vd, index);
379 } else {
380 return new VmovRegCoreSB(machInst, rt,
381 (IntRegIndex)vd, index);
382 }
383 case 16:
384 if (u) {
385 return new VmovRegCoreUH(machInst, rt,
386 (IntRegIndex)vd, index);
387 } else {
388 return new VmovRegCoreSH(machInst, rt,
389 (IntRegIndex)vd, index);
390 }
391 case 32:
392 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
393 }
|
285 }
286 return new Unknown(machInst);
287 }
288 '''
289}};
| 394 }
395 return new Unknown(machInst);
396 }
397 '''
398}};
|