fp.isa (8607:5fb918115c07) | fp.isa (9550:e0e2c8f83d08) |
---|---|
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 1556 unchanged lines hidden (view full) --- 1565 return decodeNeonUTwoMiscUSReg<NVqmovun>( 1566 size, machInst, vd, vm); 1567 } else { 1568 return decodeNeonSTwoMiscUSReg<NVqmovn>( 1569 size, machInst, vd, vm); 1570 } 1571 case 0x6: 1572 if (b == 0xc) { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 1556 unchanged lines hidden (view full) --- 1565 return decodeNeonUTwoMiscUSReg<NVqmovun>( 1566 size, machInst, vd, vm); 1567 } else { 1568 return decodeNeonSTwoMiscUSReg<NVqmovn>( 1569 size, machInst, vd, vm); 1570 } 1571 case 0x6: 1572 if (b == 0xc) { |
1573 const IntRegIndex vd = 1574 (IntRegIndex)(2 * (bits(machInst, 15, 12) | 1575 (bits(machInst, 22) << 4))); 1576 const IntRegIndex vm = 1577 (IntRegIndex)(2 * (bits(machInst, 3, 0) | 1578 (bits(machInst, 5) << 4))); 1579 unsigned size = bits(machInst, 19, 18); | |
1580 return decodeNeonSTwoShiftUSReg<NVshll>( 1581 size, machInst, vd, vm, 8 << size); 1582 } else { 1583 return new Unknown(machInst); 1584 } 1585 case 0xc: 1586 case 0xe: 1587 if (b == 0x18) { --- 273 unchanged lines hidden (view full) --- 1861 } else if (bits(opcode, 1, 0) == 0x3) { 1862 return new VLdmStm(machInst, rn, vd, single, 1863 false, true, true, offset); 1864 } 1865 // Fall through on purpose 1866 case 0x3: 1867 const bool up = (bits(machInst, 23) == 1); 1868 const uint32_t imm = bits(machInst, 7, 0) << 2; | 1573 return decodeNeonSTwoShiftUSReg<NVshll>( 1574 size, machInst, vd, vm, 8 << size); 1575 } else { 1576 return new Unknown(machInst); 1577 } 1578 case 0xc: 1579 case 0xe: 1580 if (b == 0x18) { --- 273 unchanged lines hidden (view full) --- 1854 } else if (bits(opcode, 1, 0) == 0x3) { 1855 return new VLdmStm(machInst, rn, vd, single, 1856 false, true, true, offset); 1857 } 1858 // Fall through on purpose 1859 case 0x3: 1860 const bool up = (bits(machInst, 23) == 1); 1861 const uint32_t imm = bits(machInst, 7, 0) << 2; |
1869 RegIndex vd; | |
1870 if (single) { 1871 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1872 (bits(machInst, 22))); 1873 } else { 1874 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1875 (bits(machInst, 22) << 5)); 1876 } 1877 if (bits(opcode, 1, 0) == 0x0) { --- 630 unchanged lines hidden --- | 1862 if (single) { 1863 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1864 (bits(machInst, 22))); 1865 } else { 1866 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1867 (bits(machInst, 22) << 5)); 1868 } 1869 if (bits(opcode, 1, 0) == 0x0) { --- 630 unchanged lines hidden --- |