fp.isa (7380:baee640ca6a4) | fp.isa (7389:714dea5b5298) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 468 unchanged lines hidden (view full) --- 477 StaticInstPtr 478 decodeVfpData(ExtMachInst machInst) 479 { 480 const uint32_t opc1 = bits(machInst, 23, 20); 481 const uint32_t opc2 = bits(machInst, 19, 16); 482 const uint32_t opc3 = bits(machInst, 7, 6); 483 //const uint32_t opc4 = bits(machInst, 3, 0); 484 const bool single = (bits(machInst, 8) == 0); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 468 unchanged lines hidden (view full) --- 477 StaticInstPtr 478 decodeVfpData(ExtMachInst machInst) 479 { 480 const uint32_t opc1 = bits(machInst, 23, 20); 481 const uint32_t opc2 = bits(machInst, 19, 16); 482 const uint32_t opc3 = bits(machInst, 7, 6); 483 //const uint32_t opc4 = bits(machInst, 3, 0); 484 const bool single = (bits(machInst, 8) == 0); |
485 // Used to select between vcmp and vcmpe. 486 const bool e = (bits(machInst, 7) == 1); |
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485 IntRegIndex vd; 486 IntRegIndex vm; 487 IntRegIndex vn; 488 if (single) { 489 vd = (IntRegIndex)(bits(machInst, 22) | 490 (bits(machInst, 15, 12) << 1)); 491 vm = (IntRegIndex)(bits(machInst, 5) | 492 (bits(machInst, 3, 0) << 1)); --- 143 unchanged lines hidden (view full) --- 636 } 637 } 638 case 0x2: 639 case 0x3: 640 // Between half and single precision. 641 return new WarnUnimplemented("vcvtb, vcvtt", machInst); 642 case 0x4: 643 if (single) { | 487 IntRegIndex vd; 488 IntRegIndex vm; 489 IntRegIndex vn; 490 if (single) { 491 vd = (IntRegIndex)(bits(machInst, 22) | 492 (bits(machInst, 15, 12) << 1)); 493 vm = (IntRegIndex)(bits(machInst, 5) | 494 (bits(machInst, 3, 0) << 1)); --- 143 unchanged lines hidden (view full) --- 638 } 639 } 640 case 0x2: 641 case 0x3: 642 // Between half and single precision. 643 return new WarnUnimplemented("vcvtb, vcvtt", machInst); 644 case 0x4: 645 if (single) { |
644 return new VcmpS(machInst, vd, vm); | 646 if (e) { 647 return new VcmpeS(machInst, vd, vm); 648 } else { 649 return new VcmpS(machInst, vd, vm); 650 } |
645 } else { | 651 } else { |
646 return new VcmpD(machInst, vd, vm); | 652 if (e) { 653 return new VcmpeD(machInst, vd, vm); 654 } else { 655 return new VcmpD(machInst, vd, vm); 656 } |
647 } 648 case 0x5: 649 if (single) { | 657 } 658 case 0x5: 659 if (single) { |
650 return new VcmpZeroS(machInst, vd, 0); | 660 if (e) { 661 return new VcmpeZeroS(machInst, vd, 0); 662 } else { 663 return new VcmpZeroS(machInst, vd, 0); 664 } |
651 } else { | 665 } else { |
652 return new VcmpZeroD(machInst, vd, 0); | 666 if (e) { 667 return new VcmpeZeroD(machInst, vd, 0); 668 } else { 669 return new VcmpZeroD(machInst, vd, 0); 670 } |
653 } 654 case 0x7: 655 if (opc3 == 0x3) { 656 if (single) { 657 vm = (IntRegIndex)(bits(machInst, 5) | 658 (bits(machInst, 3, 0) << 1)); 659 return new VcvtFpSFpD(machInst, vd, vm); 660 } else { --- 157 unchanged lines hidden --- | 671 } 672 case 0x7: 673 if (opc3 == 0x3) { 674 if (single) { 675 vm = (IntRegIndex)(bits(machInst, 5) | 676 (bits(machInst, 3, 0) << 1)); 677 return new VcvtFpSFpD(machInst, vd, vm); 678 } else { --- 157 unchanged lines hidden --- |