fp.isa (7376:3b781776b2d9) | fp.isa (7377:ce388054b481) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 626 unchanged lines hidden (view full) --- 635 machInst, vd, vm, true); 636 } 637 } 638 case 0x2: 639 case 0x3: 640 // Between half and single precision. 641 return new WarnUnimplemented("vcvtb, vcvtt", machInst); 642 case 0x4: | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 626 unchanged lines hidden (view full) --- 635 machInst, vd, vm, true); 636 } 637 } 638 case 0x2: 639 case 0x3: 640 // Between half and single precision. 641 return new WarnUnimplemented("vcvtb, vcvtt", machInst); 642 case 0x4: |
643 if (single) { 644 return new VcmpS(machInst, vd, vm); 645 } else { 646 return new VcmpD(machInst, vd, vm); 647 } |
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643 case 0x5: | 648 case 0x5: |
644 return new WarnUnimplemented("vcmp, vcmpe", machInst); | 649 if (single) { 650 return new VcmpZeroS(machInst, vd, 0); 651 } else { 652 return new VcmpZeroD(machInst, vd, 0); 653 } |
645 case 0x7: 646 if (opc3 == 0x3) { 647 if (single) { 648 vm = (IntRegIndex)(bits(machInst, 5) | 649 (bits(machInst, 3, 0) << 1)); 650 return new VcvtFpSFpD(machInst, vd, vm); 651 } else { 652 vd = (IntRegIndex)(bits(machInst, 22) | --- 60 unchanged lines hidden --- | 654 case 0x7: 655 if (opc3 == 0x3) { 656 if (single) { 657 vm = (IntRegIndex)(bits(machInst, 5) | 658 (bits(machInst, 3, 0) << 1)); 659 return new VcvtFpSFpD(machInst, vd, vm); 660 } else { 661 vd = (IntRegIndex)(bits(machInst, 22) | --- 60 unchanged lines hidden --- |