fp.isa (7346:b8826d184ea3) | fp.isa (7356:ff7e89d1a964) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 134 unchanged lines hidden (view full) --- 143 "predicate_test": predicateTest}, 144 flags) 145 header_output = BasicDeclare.subst(iop) 146 decoder_output = BasicConstructor.subst(iop) 147 decode_block = BasicDecode.subst(iop) 148 exec_output = FPAExecute.subst(iop) 149}}; 150 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 134 unchanged lines hidden (view full) --- 143 "predicate_test": predicateTest}, 144 flags) 145 header_output = BasicDeclare.subst(iop) 146 decoder_output = BasicConstructor.subst(iop) 147 decode_block = BasicDecode.subst(iop) 148 exec_output = FPAExecute.subst(iop) 149}}; 150 |
151def format ExtensionRegLoadStore() {{ 152 decode_block = ''' | 151let {{ 152 header_output = ''' 153 StaticInstPtr 154 decodeExtensionRegLoadStore(ExtMachInst machInst); 155 ''' 156 decoder_output = ''' 157 StaticInstPtr 158 decodeExtensionRegLoadStore(ExtMachInst machInst) |
153 { 154 const uint32_t opcode = bits(machInst, 24, 20); 155 const uint32_t offset = bits(machInst, 7, 0); 156 const bool single = (bits(machInst, 8) == 0); 157 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 158 RegIndex vd; 159 if (single) { 160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | --- 111 unchanged lines hidden (view full) --- 272 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 273 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 274 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 275 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 276 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 277 } 278}}; 279 | 159 { 160 const uint32_t opcode = bits(machInst, 24, 20); 161 const uint32_t offset = bits(machInst, 7, 0); 162 const bool single = (bits(machInst, 8) == 0); 163 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 164 RegIndex vd; 165 if (single) { 166 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | --- 111 unchanged lines hidden (view full) --- 278 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 279 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 280 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 281 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 282 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 283 } 284}}; 285 |
280def format ShortFpTransfer() {{ | 286def format ExtensionRegLoadStore() {{ |
281 decode_block = ''' | 287 decode_block = ''' |
288 return decodeExtensionRegLoadStore(machInst); 289 ''' 290}}; 291 292let {{ 293 header_output = ''' 294 StaticInstPtr 295 decodeShortFpTransfer(ExtMachInst machInst); 296 ''' 297 decoder_output = ''' 298 StaticInstPtr 299 decodeShortFpTransfer(ExtMachInst machInst) |
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282 { 283 const uint32_t l = bits(machInst, 20); 284 const uint32_t c = bits(machInst, 8); 285 const uint32_t a = bits(machInst, 23, 21); 286 const uint32_t b = bits(machInst, 6, 5); 287 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 288 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 289 return new Unknown(machInst); --- 148 unchanged lines hidden (view full) --- 438 case 32: 439 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 440 } 441 } 442 return new Unknown(machInst); 443 } 444 ''' 445}}; | 300 { 301 const uint32_t l = bits(machInst, 20); 302 const uint32_t c = bits(machInst, 8); 303 const uint32_t a = bits(machInst, 23, 21); 304 const uint32_t b = bits(machInst, 6, 5); 305 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 306 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 307 return new Unknown(machInst); --- 148 unchanged lines hidden (view full) --- 456 case 32: 457 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 458 } 459 } 460 return new Unknown(machInst); 461 } 462 ''' 463}}; |
464 465def format ShortFpTransfer() {{ 466 decode_block = ''' 467 return decodeShortFpTransfer(machInst); 468 ''' 469}}; |
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