fp.isa (7337:41379badc620) | fp.isa (7346:b8826d184ea3) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 205 unchanged lines hidden (view full) --- 214 return new VLdmStm(machInst, rn, vd, single, 215 false, true, false, offset); 216 } else if (bits(opcode, 1, 0) == 0x3) { 217 return new VLdmStm(machInst, rn, vd, single, 218 false, true, true, offset); 219 } 220 // Fall through on purpose 221 case 0x3: | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 205 unchanged lines hidden (view full) --- 214 return new VLdmStm(machInst, rn, vd, single, 215 false, true, false, offset); 216 } else if (bits(opcode, 1, 0) == 0x3) { 217 return new VLdmStm(machInst, rn, vd, single, 218 false, true, true, offset); 219 } 220 // Fall through on purpose 221 case 0x3: |
222 const bool up = (bits(machInst, 23) == 1); 223 const uint32_t imm = bits(machInst, 7, 0) << 2; 224 RegIndex vd; 225 if (single) { 226 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 227 (bits(machInst, 22))); 228 } else { 229 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 230 (bits(machInst, 22) << 5)); 231 } |
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222 if (bits(opcode, 1, 0) == 0x0) { | 232 if (bits(opcode, 1, 0) == 0x0) { |
223 return new WarnUnimplemented("vstr", machInst); | 233 if (single) { 234 if (up) { 235 return new %(vstr_us)s(machInst, vd, rn, up, imm); 236 } else { 237 return new %(vstr_s)s(machInst, vd, rn, up, imm); 238 } 239 } else { 240 if (up) { 241 return new %(vstr_ud)s(machInst, vd, vd + 1, 242 rn, up, imm); 243 } else { 244 return new %(vstr_d)s(machInst, vd, vd + 1, 245 rn, up, imm); 246 } 247 } |
224 } else if (bits(opcode, 1, 0) == 0x1) { | 248 } else if (bits(opcode, 1, 0) == 0x1) { |
225 const bool up = (bits(machInst, 23) == 1); 226 const uint32_t imm = bits(machInst, 7, 0) << 2; 227 RegIndex vd; | |
228 if (single) { | 249 if (single) { |
229 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 230 (bits(machInst, 22))); | |
231 if (up) { 232 return new %(vldr_us)s(machInst, vd, rn, up, imm); 233 } else { 234 return new %(vldr_s)s(machInst, vd, rn, up, imm); 235 } 236 } else { | 250 if (up) { 251 return new %(vldr_us)s(machInst, vd, rn, up, imm); 252 } else { 253 return new %(vldr_s)s(machInst, vd, rn, up, imm); 254 } 255 } else { |
237 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 238 (bits(machInst, 22) << 5)); | |
239 if (up) { 240 return new %(vldr_ud)s(machInst, vd, vd + 1, 241 rn, up, imm); 242 } else { 243 return new %(vldr_d)s(machInst, vd, vd + 1, 244 rn, up, imm); 245 } 246 } 247 } 248 } 249 return new Unknown(machInst); 250 } 251 ''' % { 252 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 253 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 254 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), | 256 if (up) { 257 return new %(vldr_ud)s(machInst, vd, vd + 1, 258 rn, up, imm); 259 } else { 260 return new %(vldr_d)s(machInst, vd, vd + 1, 261 rn, up, imm); 262 } 263 } 264 } 265 } 266 return new Unknown(machInst); 267 } 268 ''' % { 269 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 270 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 271 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), |
255 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False) | 272 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 273 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 274 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 275 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 276 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) |
256 } 257}}; 258 259def format ShortFpTransfer() {{ 260 decode_block = ''' 261 { 262 const uint32_t l = bits(machInst, 20); 263 const uint32_t c = bits(machInst, 8); --- 161 unchanged lines hidden --- | 277 } 278}}; 279 280def format ShortFpTransfer() {{ 281 decode_block = ''' 282 { 283 const uint32_t l = bits(machInst, 20); 284 const uint32_t c = bits(machInst, 8); --- 161 unchanged lines hidden --- |