fp.isa (13169:eb3b2bea4231) | fp.isa (13738:84439021dcf6) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010-2011, 2016-2018 ARM Limited | 3// Copyright (c) 2010-2011, 2016-2019 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 1984 unchanged lines hidden (view full) --- 1996}}; 1997 1998let {{ 1999 header_output = ''' 2000 StaticInstPtr 2001 decodeShortFpTransfer(ExtMachInst machInst); 2002 ''' 2003 decoder_output = ''' | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 1984 unchanged lines hidden (view full) --- 1996}}; 1997 1998let {{ 1999 header_output = ''' 2000 StaticInstPtr 2001 decodeShortFpTransfer(ExtMachInst machInst); 2002 ''' 2003 decoder_output = ''' |
2004 IntRegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt) 2005 { 2006 if (!isInt and size == 3) { 2007 return (IntRegIndex)((bits(machInst, 22) << 5) | 2008 (bits(machInst, 15, 12) << 1)); 2009 } else { 2010 return (IntRegIndex)(bits(machInst, 22) | 2011 (bits(machInst, 15, 12) << 1)); 2012 } 2013 } 2014 IntRegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt) 2015 { 2016 if (!isInt and size == 3) { 2017 return (IntRegIndex)((bits(machInst, 5) << 5) | 2018 (bits(machInst, 3, 0) << 1)); 2019 } else { 2020 return (IntRegIndex)(bits(machInst, 5) | 2021 (bits(machInst, 3, 0) << 1)); 2022 } 2023 } |
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2004 StaticInstPtr 2005 decodeShortFpTransfer(ExtMachInst machInst) 2006 { 2007 const uint32_t l = bits(machInst, 20); 2008 const uint32_t c = bits(machInst, 8); 2009 const uint32_t a = bits(machInst, 23, 21); 2010 const uint32_t b = bits(machInst, 6, 5); | 2024 StaticInstPtr 2025 decodeShortFpTransfer(ExtMachInst machInst) 2026 { 2027 const uint32_t l = bits(machInst, 20); 2028 const uint32_t c = bits(machInst, 8); 2029 const uint32_t a = bits(machInst, 23, 21); 2030 const uint32_t b = bits(machInst, 6, 5); |
2031 const uint32_t o1 = bits(machInst, 18); |
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2011 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 2012 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 2013 // Determine if this is backported aarch64 FP instruction 2014 const bool b31_b24 = bits(machInst, 31, 24) == 0xFE; 2015 const bool b23 = bits(machInst, 23); | 2032 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 2033 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 2034 // Determine if this is backported aarch64 FP instruction 2035 const bool b31_b24 = bits(machInst, 31, 24) == 0xFE; 2036 const bool b23 = bits(machInst, 23); |
2016 const bool b21_b18 = bits(machInst, 21, 18) == 0xE; | 2037 const bool b21_b19 = bits(machInst, 21, 19) == 0x7; |
2017 const bool b11_b9 = bits(machInst, 11, 9) == 0x5; | 2038 const bool b11_b9 = bits(machInst, 11, 9) == 0x5; |
2018 const bool sz = bits(machInst, 8); 2019 const bool b7_b6 = bits(machInst, 7, 6) == 0x1; 2020 const bool b6 = bits(machInst, 6) == 0x0; | 2039 const uint32_t size = bits(machInst, 9, 8); 2040 const bool op3 = bits(machInst, 6); |
2021 const bool b4 = bits(machInst, 4) == 0x0; | 2041 const bool b4 = bits(machInst, 4) == 0x0; |
2022 if (b31_b24 && b23 && b21_b18 && b11_b9 && b7_b6 && b4) { 2023 // VINT* Integer Rounding Instructon 2024 const uint32_t rm = bits(machInst, 17, 16); 2025 2026 if (sz) { 2027 const IntRegIndex vd = 2028 (IntRegIndex)((bits(machInst, 22) << 5) | 2029 (bits(machInst, 15, 12) << 1)); 2030 const IntRegIndex vm = 2031 (IntRegIndex)((bits(machInst, 5) << 5) | 2032 (bits(machInst, 3, 0) << 1)); 2033 switch(rm) { 2034 case 0x0: 2035 return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm, 2036 true); 2037 case 0x1: 2038 return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm, 2039 true); 2040 case 0x2: 2041 return decodeVfpRegRegOp<VRIntPD>(machInst, vd, vm, 2042 true); 2043 case 0x3: 2044 return decodeVfpRegRegOp<VRIntMD>(machInst, vd, vm, 2045 true); 2046 default: return new Unknown(machInst); 2047 } 2048 } else { 2049 const IntRegIndex vd = 2050 (IntRegIndex)(bits(machInst, 22) | 2051 (bits(machInst, 15, 12) << 1)); 2052 const IntRegIndex vm = 2053 (IntRegIndex)(bits(machInst, 5) | 2054 (bits(machInst, 3, 0) << 1)); 2055 switch(rm) { 2056 case 0x0: 2057 return decodeVfpRegRegOp<VRIntAS>(machInst, vd, vm, 2058 false); 2059 case 0x1: 2060 return decodeVfpRegRegOp<VRIntNS>(machInst, vd, vm, 2061 false); 2062 case 0x2: 2063 return decodeVfpRegRegOp<VRIntPS>(machInst, vd, vm, 2064 false); 2065 case 0x3: 2066 return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm, 2067 false); 2068 default: return new Unknown(machInst); 2069 } 2070 } 2071 } else if (b31_b24 && !b23 && b11_b9 && b6 && b4){ | 2042 const uint32_t rm = bits(machInst, 17, 16); 2043 IntRegIndex vd = decodeFpVd(machInst, size, false); 2044 IntRegIndex vm = decodeFpVm(machInst, size, false); 2045 IntRegIndex vdInt = decodeFpVd(machInst, size, true); 2046 if (b31_b24 && b23 && b21_b19 && b11_b9 && op3 && b4) { 2047 if (o1 == 0) { 2048 // VINT* Integer Rounding Instruction 2049 if (size == 3) { 2050 switch(rm) { 2051 case 0x0: 2052 return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm, 2053 true); 2054 case 0x1: 2055 return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm, 2056 true); 2057 case 0x2: 2058 return decodeVfpRegRegOp<VRIntPD>(machInst, vd, vm, 2059 true); 2060 case 0x3: 2061 return decodeVfpRegRegOp<VRIntMD>(machInst, vd, vm, 2062 true); 2063 default: return new Unknown(machInst); 2064 } 2065 } else { 2066 switch(rm) { 2067 case 0x0: 2068 return decodeVfpRegRegOp<VRIntAS>(machInst, vd, vm, 2069 false); 2070 case 0x1: 2071 return decodeVfpRegRegOp<VRIntNS>(machInst, vd, vm, 2072 false); 2073 case 0x2: 2074 return decodeVfpRegRegOp<VRIntPS>(machInst, vd, vm, 2075 false); 2076 case 0x3: 2077 return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm, 2078 false); 2079 default: return new Unknown(machInst); 2080 } 2081 } 2082 } else { 2083 const bool op = bits(machInst, 7); 2084 switch(rm) { 2085 case 0x0: 2086 switch(size) { 2087 case 0x0: 2088 return new Unknown(machInst); 2089 case 0x1: 2090 return new FailUnimplemented( 2091 "vcvta.u32.f16", machInst); 2092 case 0x2: 2093 if (op) { 2094 return new VcvtaFpSIntS(machInst, vdInt, vm); 2095 } else { 2096 return new VcvtaFpUIntS(machInst, vdInt, vm); 2097 } 2098 case 0x3: 2099 if (op) { 2100 return new VcvtaFpSIntD(machInst, vdInt, vm); 2101 } else { 2102 return new VcvtaFpUIntD(machInst, vdInt, vm); 2103 } 2104 } 2105 case 0x1: 2106 switch(size) { 2107 case 0x0: 2108 return new Unknown(machInst); 2109 case 0x1: 2110 return new FailUnimplemented( 2111 "vcvtn.u32.f16", machInst); 2112 case 0x2: 2113 if (op) { 2114 return new VcvtnFpSIntS(machInst, vdInt, vm); 2115 } else { 2116 return new VcvtnFpUIntS(machInst, vdInt, vm); 2117 } 2118 case 0x3: 2119 if (op) { 2120 return new VcvtnFpSIntD(machInst, vdInt, vm); 2121 } else { 2122 return new VcvtnFpUIntD(machInst, vdInt, vm); 2123 } 2124 } 2125 case 0x2: 2126 switch(size) { 2127 case 0x0: 2128 return new Unknown(machInst); 2129 case 0x1: 2130 return new FailUnimplemented( 2131 "vcvtp.u32.f16", machInst); 2132 case 0x2: 2133 if (op) { 2134 return new VcvtpFpSIntS(machInst, vdInt, vm); 2135 } else { 2136 return new VcvtpFpUIntS(machInst, vdInt, vm); 2137 } 2138 case 0x3: 2139 if (op) { 2140 return new VcvtpFpSIntD(machInst, vdInt, vm); 2141 } else { 2142 return new VcvtpFpUIntD(machInst, vdInt, vm); 2143 } 2144 } 2145 case 0x3: 2146 switch(size) { 2147 case 0x0: 2148 return new Unknown(machInst); 2149 case 0x1: 2150 return new FailUnimplemented( 2151 "vcvtm.u32.f16", machInst); 2152 case 0x2: 2153 if (op) { 2154 return new VcvtmFpSIntS(machInst, vdInt, vm); 2155 } else { 2156 return new VcvtmFpUIntS(machInst, vdInt, vm); 2157 } 2158 case 0x3: 2159 if (op) { 2160 return new VcvtmFpSIntD(machInst, vdInt, vm); 2161 } else { 2162 return new VcvtmFpUIntD(machInst, vdInt, vm); 2163 } 2164 } 2165 } 2166 } 2167 } else if (b31_b24 && !b23 && b11_b9 && !op3 && b4){ |
2072 // VSEL* floating point conditional select 2073 2074 ConditionCode cond; 2075 switch(bits(machInst, 21, 20)) { 2076 case 0x0: cond = COND_EQ; break; 2077 case 0x1: cond = COND_VS; break; 2078 case 0x2: cond = COND_GE; break; 2079 case 0x3: cond = COND_GT; break; 2080 } 2081 | 2168 // VSEL* floating point conditional select 2169 2170 ConditionCode cond; 2171 switch(bits(machInst, 21, 20)) { 2172 case 0x0: cond = COND_EQ; break; 2173 case 0x1: cond = COND_VS; break; 2174 case 0x2: cond = COND_GE; break; 2175 case 0x3: cond = COND_GT; break; 2176 } 2177 |
2082 if (sz) { 2083 const IntRegIndex vd = 2084 (IntRegIndex)((bits(machInst, 22) << 5) | 2085 (bits(machInst, 15, 12) << 1)); 2086 const IntRegIndex vm = 2087 (IntRegIndex)((bits(machInst, 5) << 5) | 2088 (bits(machInst, 3, 0) << 1)); | 2178 if (size == 3) { |
2089 const IntRegIndex vn = 2090 (IntRegIndex)((bits(machInst, 7) << 5) | 2091 (bits(machInst, 19, 16) << 1)); 2092 return new VselD(machInst, vd, vn, vm, cond); 2093 } else { | 2179 const IntRegIndex vn = 2180 (IntRegIndex)((bits(machInst, 7) << 5) | 2181 (bits(machInst, 19, 16) << 1)); 2182 return new VselD(machInst, vd, vn, vm, cond); 2183 } else { |
2094 const IntRegIndex vd = 2095 (IntRegIndex)(bits(machInst, 22) | 2096 (bits(machInst, 15, 12) << 1)); 2097 const IntRegIndex vm = 2098 (IntRegIndex)(bits(machInst, 5) | 2099 (bits(machInst, 3, 0) << 1)); | |
2100 const IntRegIndex vn = 2101 (IntRegIndex)((bits(machInst, 19, 16) << 1) | 2102 bits(machInst, 7)); 2103 return new VselS(machInst, vd, vn, vm, cond); 2104 } 2105 } else { 2106 return new Unknown(machInst); 2107 } --- 605 unchanged lines hidden --- | 2184 const IntRegIndex vn = 2185 (IntRegIndex)((bits(machInst, 19, 16) << 1) | 2186 bits(machInst, 7)); 2187 return new VselS(machInst, vd, vn, vm, cond); 2188 } 2189 } else { 2190 return new Unknown(machInst); 2191 } --- 605 unchanged lines hidden --- |