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1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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547 vn = (bits(machInst, 7) << 5) |
548 (bits(machInst, 19, 16) << 1);
549 return new VsubD(machInst, (IntRegIndex)vd,
550 (IntRegIndex)vn, (IntRegIndex)vm);
551 }
552 }
553 case 0x8:
554 if ((opc3 & 0x1) == 0) {
555 return new WarnUnimplemented("vdiv", machInst);
556 }
557 break;
558 case 0xb:
559 if ((opc3 & 0x1) == 0) {
560 uint32_t vd;
561 const uint32_t baseImm =
562 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
563 if (bits(machInst, 8) == 0) {

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619 vd = (bits(machInst, 22) << 5) |
620 (bits(machInst, 15, 12) << 1);
621 vm = (bits(machInst, 5) << 5) |
622 (bits(machInst, 3, 0) << 1);
623 return new VnegD(machInst,
624 (IntRegIndex)vd, (IntRegIndex)vm);
625 }
626 } else {
627 return new WarnUnimplemented("vsqrt", machInst);
628 }
629 case 0x2:
630 case 0x3:
631 // Between half and single precision.
632 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
633 case 0x4:
634 case 0x5:
635 return new WarnUnimplemented("vcmp, vcmpe", machInst);

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