1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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148 exec_output = FPAExecute.subst(iop)
149}};
150
151def format ExtensionRegLoadStore() {{
152 decode_block = '''
153 {
154 const uint32_t opcode = bits(machInst, 24, 20);
155 const uint32_t offset = bits(machInst, 7, 0);
156 const bool single = bits(machInst, 22);
157 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
158 RegIndex vd;
159 if (single) {
160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
161 bits(machInst, 22));
162 } else {
163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
164 (bits(machInst, 22) << 5));

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172 break;
173 }
174 const IntRegIndex rt =
175 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
176 const IntRegIndex rt2 =
177 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
178 const bool op = bits(machInst, 20);
179 uint32_t vm;
180 if (bits(machInst, 8) == 0) {
181 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
182 } else {
183 vm = (bits(machInst, 3, 0) << 1) |
184 (bits(machInst, 5) << 5);
185 }
186 if (op) {
187 return new Vmov2Core2Reg(machInst, rt, rt2,
188 (IntRegIndex)vm);

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217 return new VLdmStm(machInst, rn, vd, single,
218 false, true, true, offset);
219 }
220 // Fall through on purpose
221 case 0x3:
222 if (bits(opcode, 1, 0) == 0x0) {
223 return new WarnUnimplemented("vstr", machInst);
224 } else if (bits(opcode, 1, 0) == 0x1) {
225 return new WarnUnimplemented("vldr", machInst);
226 }
227 }
228 return new Unknown(machInst);
229 }
230 '''
231}};
232
233def format ShortFpTransfer() {{
234 decode_block = '''
235 {
236 const uint32_t l = bits(machInst, 20);
237 const uint32_t c = bits(machInst, 8);
238 const uint32_t a = bits(machInst, 23, 21);

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