1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 151 unchanged lines hidden (view full) ---

160 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
161 bits(machInst, 22));
162 } else {
163 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
164 (bits(machInst, 22) << 5));
165 }
166 switch (bits(opcode, 4, 3)) {
167 case 0x0:
168 if (bits(opcode, 4, 1) == 0x2) {
169 return new WarnUnimplemented("core-to-extension-transfer",
170 machInst);
171 }
172 break;
173 case 0x1:
174 switch (bits(opcode, 1, 0)) {
175 case 0x0:
176 return new VLdmStm(machInst, rn, vd, single,
177 true, false, false, offset);
178 case 0x1:

--- 37 unchanged lines hidden (view full) ---

216 const uint32_t a = bits(machInst, 23, 21);
217 const uint32_t b = bits(machInst, 6, 5);
218 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
219 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
220 return new Unknown(machInst);
221 }
222 if (l == 0 && c == 0) {
223 if (a == 0) {
224 // A8-648
225 return new WarnUnimplemented("vmov", machInst);
226 } else if (a == 0x7) {
227 const IntRegIndex rt =
228 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
229 uint32_t specReg = bits(machInst, 19, 16);
230 switch (specReg) {
231 case 0:
232 specReg = MISCREG_FPSID;
233 break;

--- 5 unchanged lines hidden (view full) ---

239 break;
240 default:
241 return new Unknown(machInst);
242 }
243 return new Vmsr(machInst, (IntRegIndex)specReg, rt);
244 }
245 } else if (l == 0 && c == 1) {
246 if (bits(a, 2) == 0) {
247 // A8-644
248 return new WarnUnimplemented("vmov", machInst);
249 } else if (bits(b, 1) == 0) {
250 // A8-594
251 return new WarnUnimplemented("vdup", machInst);
252 }
253 } else if (l == 1 && c == 0) {
254 if (a == 0) {
255 // A8-648
256 return new WarnUnimplemented("vmov", machInst);
257 } else if (a == 7) {
258 const IntRegIndex rt =
259 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
260 uint32_t specReg = bits(machInst, 19, 16);
261 switch (specReg) {
262 case 0:
263 specReg = MISCREG_FPSID;
264 break;

--- 10 unchanged lines hidden (view full) ---

275 specReg = MISCREG_FPEXC;
276 break;
277 default:
278 return new Unknown(machInst);
279 }
280 return new Vmrs(machInst, rt, (IntRegIndex)specReg);
281 }
282 } else {
283 // A8-646
284 return new WarnUnimplemented("vmov", machInst);
285 }
286 return new Unknown(machInst);
287 }
288 '''
289}};