1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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2029 if (!isInt and size == 3) {
2030 return (IntRegIndex)((bits(machInst, 22) << 5) |
2031 (bits(machInst, 15, 12) << 1));
2032 } else {
2033 return (IntRegIndex)(bits(machInst, 22) |
2034 (bits(machInst, 15, 12) << 1));
2035 }
2036 }
2037 IntRegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt)
2038 {
2039 if (!isInt and size == 3) {
2040 return (IntRegIndex)((bits(machInst, 5) << 5) |
2041 (bits(machInst, 3, 0) << 1));
2042 } else {
2043 return (IntRegIndex)(bits(machInst, 5) |
2044 (bits(machInst, 3, 0) << 1));
2045 }
2046 }
2047 StaticInstPtr
2048 decodeShortFpTransfer(ExtMachInst machInst)
2049 {
2050 const uint32_t l = bits(machInst, 20);
2051 const uint32_t c = bits(machInst, 8);
2052 const uint32_t a = bits(machInst, 23, 21);
2053 const uint32_t q = bits(machInst, 6, 5);
2054 const uint32_t o1 = bits(machInst, 18);
2055 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
2056 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
2057 // Determine if this is backported aarch64 FP instruction
2058 const bool b31_b24 = bits(machInst, 31, 24) == 0xFE;
2059 const bool b23 = bits(machInst, 23);
2060 const bool b21_b19 = bits(machInst, 21, 19) == 0x7;
2061 const bool b11_b9 = bits(machInst, 11, 9) == 0x5;
2062 const uint32_t size = bits(machInst, 9, 8);
2063 const bool op3 = bits(machInst, 6);
2064 const bool b4 = bits(machInst, 4) == 0x0;
2065 const uint32_t rm = bits(machInst, 17, 16);
2066 IntRegIndex vd = decodeFpVd(machInst, size, false);
2067 IntRegIndex vm = decodeFpVm(machInst, size, false);
2068 IntRegIndex vdInt = decodeFpVd(machInst, size, true);
2069 if (b31_b24 && b23 && b21_b19 && b11_b9 && op3 && b4) {
2070 if (o1 == 0) {
2071 // VINT* Integer Rounding Instruction
2072 if (size == 3) {
2073 switch(rm) {
2074 case 0x0:
2075 return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm,
2076 true);
2077 case 0x1:
2078 return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm,
2079 true);

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2100 return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm,
2101 false);
2102 default: return new Unknown(machInst);
2103 }
2104 }
2105 } else {
2106 const bool op = bits(machInst, 7);
2107 switch(rm) {
2108 case 0x0:
2109 switch(size) {
2110 case 0x0:
2111 return new Unknown(machInst);
2112 case 0x1:
2113 return new FailUnimplemented(
2114 "vcvta.u32.f16", machInst);
2115 case 0x2:
2116 if (op) {
2117 return new VcvtaFpSIntS(machInst, vdInt, vm);
2118 } else {
2119 return new VcvtaFpUIntS(machInst, vdInt, vm);
2120 }
2121 case 0x3:
2122 if (op) {
2123 return new VcvtaFpSIntD(machInst, vdInt, vm);
2124 } else {
2125 return new VcvtaFpUIntD(machInst, vdInt, vm);
2126 }
2127 default: return new Unknown(machInst);
2128 }
2129 case 0x1:
2130 switch(size) {
2131 case 0x0:
2132 return new Unknown(machInst);
2133 case 0x1:
2134 return new FailUnimplemented(
2135 "vcvtn.u32.f16", machInst);
2136 case 0x2:
2137 if (op) {
2138 return new VcvtnFpSIntS(machInst, vdInt, vm);
2139 } else {
2140 return new VcvtnFpUIntS(machInst, vdInt, vm);
2141 }
2142 case 0x3:
2143 if (op) {
2144 return new VcvtnFpSIntD(machInst, vdInt, vm);
2145 } else {
2146 return new VcvtnFpUIntD(machInst, vdInt, vm);
2147 }
2148 default: return new Unknown(machInst);
2149 }
2150 case 0x2:
2151 switch(size) {
2152 case 0x0:
2153 return new Unknown(machInst);
2154 case 0x1:
2155 return new FailUnimplemented(
2156 "vcvtp.u32.f16", machInst);
2157 case 0x2:
2158 if (op) {
2159 return new VcvtpFpSIntS(machInst, vdInt, vm);
2160 } else {
2161 return new VcvtpFpUIntS(machInst, vdInt, vm);
2162 }
2163 case 0x3:
2164 if (op) {
2165 return new VcvtpFpSIntD(machInst, vdInt, vm);
2166 } else {
2167 return new VcvtpFpUIntD(machInst, vdInt, vm);
2168 }
2169 default: return new Unknown(machInst);
2170 }
2171 case 0x3:
2172 switch(size) {
2173 case 0x0:
2174 return new Unknown(machInst);
2175 case 0x1:
2176 return new FailUnimplemented(
2177 "vcvtm.u32.f16", machInst);
2178 case 0x2:
2179 if (op) {
2180 return new VcvtmFpSIntS(machInst, vdInt, vm);
2181 } else {
2182 return new VcvtmFpUIntS(machInst, vdInt, vm);
2183 }
2184 case 0x3:
2185 if (op) {
2186 return new VcvtmFpSIntD(machInst, vdInt, vm);
2187 } else {
2188 return new VcvtmFpUIntD(machInst, vdInt, vm);
2189 }
2190 default: return new Unknown(machInst);
2191 }
2192 default: return new Unknown(machInst);
2193 }
2194 }
2195 } else if (b31_b24 && !b23 && b11_b9 && !op3 && b4){
2196 // VSEL* floating point conditional select
2197
2198 ConditionCode cond;
2199 switch(bits(machInst, 21, 20)) {
2200 case 0x0: cond = COND_EQ; break;
2201 case 0x1: cond = COND_VS; break;
2202 case 0x2: cond = COND_GE; break;
2203 case 0x3: cond = COND_GT; break;
2204 }
2205
2206 if (size == 3) {
2207 const IntRegIndex vn =
2208 (IntRegIndex)((bits(machInst, 7) << 5) |
2209 (bits(machInst, 19, 16) << 1));
2210 return new VselD(machInst, vd, vn, vm, cond);
2211 } else {
2212 const IntRegIndex vn =
2213 (IntRegIndex)((bits(machInst, 19, 16) << 1) |
2214 bits(machInst, 7));
2215 return new VselS(machInst, vd, vn, vm, cond);
2216 }
2217 } else {
2218 return new Unknown(machInst);
2219 }
2220 }
2221 if (l == 0 && c == 0) {
2222 if (a == 0) {
2223 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
2224 bits(machInst, 7);
2225 const IntRegIndex rt =
2226 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
2227 if (bits(machInst, 20) == 1) {
2228 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);

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