1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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336 }
337 '''
338
339 decoder_output += '''
340 static StaticInstPtr
341 decodeNeonThreeRegistersSameLength(ExtMachInst machInst)
342 {
343 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
344 const uint32_t a = bits(machInst, 11, 8);
345 const bool b = bits(machInst, 4);
346 const uint32_t c = bits(machInst, 21, 20);
347 const IntRegIndex vd =
348 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
349 (bits(machInst, 22) << 4)));
350 const IntRegIndex vn =
351 (IntRegIndex)(2 * (bits(machInst, 19, 16) |
352 (bits(machInst, 7) << 4)));
353 const IntRegIndex vm =
354 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
355 (bits(machInst, 5) << 4)));
356 const unsigned size = bits(machInst, 21, 20);
357 const bool q = bits(machInst, 6);
358 if (q && ((vd & 0x1) || (vn & 0x1) || (vm & 0x1)))
359 return new Unknown(machInst);
360 switch (a) {
361 case 0x0:
362 if (b) {
363 if (u) {
364 return decodeNeonUThreeReg<VqaddUD, VqaddUQ>(
365 q, size, machInst, vd, vn, vm);
366 } else {
367 return decodeNeonSThreeReg<VqaddSD, VqaddSQ>(
368 q, size, machInst, vd, vn, vm);
369 }
370 } else {
371 if (size == 3)
372 return new Unknown(machInst);
373 return decodeNeonUSThreeReg<VhaddD, VhaddQ>(
374 q, u, size, machInst, vd, vn, vm);
375 }
376 case 0x1:
377 if (!b) {
378 return decodeNeonUSThreeReg<VrhaddD, VrhaddQ>(
379 q, u, size, machInst, vd, vn, vm);
380 } else {
381 if (u) {
382 switch (c) {
383 case 0:
384 if (q) {
385 return new VeorQ<uint64_t>(machInst, vd, vn, vm);
386 } else {
387 return new VeorD<uint64_t>(machInst, vd, vn, vm);
388 }
389 case 1:
390 if (q) {

--- 12 unchanged lines hidden (view full) ---

403 return new VbifQ<uint64_t>(machInst, vd, vn, vm);
404 } else {
405 return new VbifD<uint64_t>(machInst, vd, vn, vm);
406 }
407 default:
408 M5_UNREACHABLE;
409 }
410 } else {
411 switch (c) {
412 case 0:
413 if (q) {
414 return new VandQ<uint64_t>(machInst, vd, vn, vm);
415 } else {
416 return new VandD<uint64_t>(machInst, vd, vn, vm);
417 }
418 case 1:
419 if (q) {

--- 28 unchanged lines hidden (view full) ---

448 machInst, vd, vn, vm);
449 }
450 default:
451 M5_UNREACHABLE;
452 }
453 }
454 }
455 case 0x2:
456 if (b) {
457 if (u) {
458 return decodeNeonUThreeReg<VqsubUD, VqsubUQ>(
459 q, size, machInst, vd, vn, vm);
460 } else {
461 return decodeNeonSThreeReg<VqsubSD, VqsubSQ>(
462 q, size, machInst, vd, vn, vm);
463 }
464 } else {
465 if (size == 3)
466 return new Unknown(machInst);
467 return decodeNeonUSThreeReg<VhsubD, VhsubQ>(
468 q, u, size, machInst, vd, vn, vm);
469 }
470 case 0x3:
471 if (b) {
472 return decodeNeonUSThreeReg<VcgeD, VcgeQ>(
473 q, u, size, machInst, vd, vn, vm);
474 } else {
475 return decodeNeonUSThreeReg<VcgtD, VcgtQ>(
476 q, u, size, machInst, vd, vn, vm);
477 }
478 case 0x4:
479 if (b) {
480 if (u) {
481 return decodeNeonUThreeReg<VqshlUD, VqshlUQ>(
482 q, size, machInst, vd, vm, vn);
483 } else {
484 return decodeNeonSThreeReg<VqshlSD, VqshlSQ>(
485 q, size, machInst, vd, vm, vn);
486 }
487 } else {
488 return decodeNeonUSThreeReg<VshlD, VshlQ>(
489 q, u, size, machInst, vd, vm, vn);
490 }
491 case 0x5:
492 if (b) {
493 if (u) {
494 return decodeNeonUThreeReg<VqrshlUD, VqrshlUQ>(
495 q, size, machInst, vd, vm, vn);
496 } else {
497 return decodeNeonSThreeReg<VqrshlSD, VqrshlSQ>(
498 q, size, machInst, vd, vm, vn);
499 }
500 } else {
501 return decodeNeonUSThreeReg<VrshlD, VrshlQ>(
502 q, u, size, machInst, vd, vm, vn);
503 }
504 case 0x6:
505 if (b) {
506 return decodeNeonUSThreeReg<VminD, VminQ>(
507 q, u, size, machInst, vd, vn, vm);
508 } else {
509 return decodeNeonUSThreeReg<VmaxD, VmaxQ>(
510 q, u, size, machInst, vd, vn, vm);
511 }
512 case 0x7:
513 if (b) {
514 return decodeNeonUSThreeReg<VabaD, VabaQ>(
515 q, u, size, machInst, vd, vn, vm);
516 } else {
517 if (bits(machInst, 23) == 1) {
518 if (q) {
519 return new Unknown(machInst);
520 } else {
521 return decodeNeonUSThreeUSReg<Vabdl>(
522 u, size, machInst, vd, vn, vm);
523 }
524 } else {
525 return decodeNeonUSThreeReg<VabdD, VabdQ>(
526 q, u, size, machInst, vd, vn, vm);
527 }
528 }
529 case 0x8:
530 if (b) {
531 if (u) {
532 return decodeNeonUThreeReg<VceqD, VceqQ>(
533 q, size, machInst, vd, vn, vm);
534 } else {
535 return decodeNeonUThreeReg<VtstD, VtstQ>(
536 q, size, machInst, vd, vn, vm);
537 }
538 } else {
539 if (u) {
540 return decodeNeonUThreeReg<NVsubD, NVsubQ>(
541 q, size, machInst, vd, vn, vm);
542 } else {
543 return decodeNeonUThreeReg<NVaddD, NVaddQ>(
544 q, size, machInst, vd, vn, vm);
545 }
546 }
547 case 0x9:
548 if (b) {
549 if (u) {
550 return decodeNeonUThreeReg<NVmulpD, NVmulpQ>(
551 q, size, machInst, vd, vn, vm);
552 } else {
553 return decodeNeonSThreeReg<NVmulD, NVmulQ>(
554 q, size, machInst, vd, vn, vm);
555 }
556 } else {
557 if (u) {
558 return decodeNeonUSThreeReg<NVmlsD, NVmlsQ>(
559 q, u, size, machInst, vd, vn, vm);
560 } else {
561 return decodeNeonUSThreeReg<NVmlaD, NVmlaQ>(
562 q, u, size, machInst, vd, vn, vm);
563 }
564 }
565 case 0xa:
566 if (q)
567 return new Unknown(machInst);
568 if (b) {
569 return decodeNeonUSThreeUSReg<VpminD>(
570 u, size, machInst, vd, vn, vm);
571 } else {
572 return decodeNeonUSThreeUSReg<VpmaxD>(
573 u, size, machInst, vd, vn, vm);
574 }
575 case 0xb:
576 if (b) {
577 if (u || q) {
578 return new Unknown(machInst);
579 } else {
580 return decodeNeonUThreeUSReg<NVpaddD>(
581 size, machInst, vd, vn, vm);
582 }
583 } else {
584 if (u) {
585 return decodeNeonSThreeSReg<VqrdmulhD, VqrdmulhQ>(
586 q, size, machInst, vd, vn, vm);
587 } else {
588 return decodeNeonSThreeSReg<VqdmulhD, VqdmulhQ>(
589 q, size, machInst, vd, vn, vm);
590 }
591 }
592 case 0xc:
593 if (b) {
594 if (!u) {
595 if (bits(c, 1) == 0) {
596 if (q) {
597 return new NVfmaQFp<float>(machInst, vd, vn, vm);
598 } else {
599 return new NVfmaDFp<float>(machInst, vd, vn, vm);
600 }
601 } else {
602 if (q) {
603 return new NVfmsQFp<float>(machInst, vd, vn, vm);
604 } else {
605 return new NVfmsDFp<float>(machInst, vd, vn, vm);
606 }
607 }
608 }
609 } else {
610 if (u) {
611 switch (c) {
612 case 0x0:
613 return new SHA256H(machInst, vd, vn, vm);
614 case 0x1:
615 return new SHA256H2(machInst, vd, vn, vm);
616 case 0x2:
617 return new SHA256SU1(machInst, vd, vn, vm);
618 case 0x3:
619 return new Unknown(machInst);
620 default:
621 M5_UNREACHABLE;
622 }
623 } else {
624 switch (c) {
625 case 0x0:
626 return new SHA1C(machInst, vd, vn, vm);
627 case 0x1:
628 return new SHA1P(machInst, vd, vn, vm);
629 case 0x2:
630 return new SHA1M(machInst, vd, vn, vm);
631 case 0x3:
632 return new SHA1SU0(machInst, vd, vn, vm);
633 default:
634 M5_UNREACHABLE;
635 }
636 }
637 }
638 return new Unknown(machInst);
639 case 0xd:
640 if (b) {
641 if (u) {
642 if (bits(c, 1) == 0) {
643 if (q) {
644 return new NVmulQFp<float>(machInst, vd, vn, vm);
645 } else {
646 return new NVmulDFp<float>(machInst, vd, vn, vm);
647 }
648 } else {
649 return new Unknown(machInst);
650 }
651 } else {
652 if (bits(c, 1) == 0) {
653 if (q) {
654 return new NVmlaQFp<float>(machInst, vd, vn, vm);
655 } else {
656 return new NVmlaDFp<float>(machInst, vd, vn, vm);
657 }
658 } else {
659 if (q) {
660 return new NVmlsQFp<float>(machInst, vd, vn, vm);
661 } else {
662 return new NVmlsDFp<float>(machInst, vd, vn, vm);
663 }
664 }
665 }
666 } else {
667 if (u) {
668 if (bits(c, 1) == 0) {
669 if (q) {
670 return new VpaddQFp<float>(machInst, vd, vn, vm);
671 } else {
672 return new VpaddDFp<float>(machInst, vd, vn, vm);
673 }
674 } else {
675 if (q) {
676 return new VabdQFp<float>(machInst, vd, vn, vm);
677 } else {
678 return new VabdDFp<float>(machInst, vd, vn, vm);
679 }
680 }
681 } else {
682 if (bits(c, 1) == 0) {
683 if (q) {
684 return new VaddQFp<float>(machInst, vd, vn, vm);
685 } else {
686 return new VaddDFp<float>(machInst, vd, vn, vm);
687 }
688 } else {
689 if (q) {
690 return new VsubQFp<float>(machInst, vd, vn, vm);
691 } else {
692 return new VsubDFp<float>(machInst, vd, vn, vm);
693 }
694 }
695 }
696 }
697 case 0xe:
698 if (b) {
699 if (u) {
700 if (bits(c, 1) == 0) {
701 if (q) {
702 return new VacgeQFp<float>(machInst, vd, vn, vm);
703 } else {
704 return new VacgeDFp<float>(machInst, vd, vn, vm);
705 }
706 } else {
707 if (q) {
708 return new VacgtQFp<float>(machInst, vd, vn, vm);
709 } else {
710 return new VacgtDFp<float>(machInst, vd, vn, vm);
711 }
712 }
713 } else {
714 return new Unknown(machInst);
715 }
716 } else {
717 if (u) {
718 if (bits(c, 1) == 0) {
719 if (q) {
720 return new VcgeQFp<float>(machInst, vd, vn, vm);
721 } else {
722 return new VcgeDFp<float>(machInst, vd, vn, vm);
723 }
724 } else {
725 if (q) {
726 return new VcgtQFp<float>(machInst, vd, vn, vm);
727 } else {
728 return new VcgtDFp<float>(machInst, vd, vn, vm);
729 }
730 }
731 } else {
732 if (bits(c, 1) == 0) {
733 if (q) {
734 return new VceqQFp<float>(machInst, vd, vn, vm);
735 } else {
736 return new VceqDFp<float>(machInst, vd, vn, vm);
737 }
738 } else {
739 return new Unknown(machInst);
740 }
741 }
742 }
743 case 0xf:
744 if (b) {
745 if (u) {
746 return new Unknown(machInst);
747 } else {
748 if (bits(c, 1) == 0) {
749 if (q) {
750 return new VrecpsQFp<float>(machInst, vd, vn, vm);
751 } else {
752 return new VrecpsDFp<float>(machInst, vd, vn, vm);
753 }
754 } else {
755 if (q) {
756 return new VrsqrtsQFp<float>(machInst, vd, vn, vm);
757 } else {
758 return new VrsqrtsDFp<float>(machInst, vd, vn, vm);
759 }
760 }
761 }
762 } else {
763 if (u) {
764 if (bits(c, 1) == 0) {
765 if (q) {
766 return new VpmaxQFp<float>(machInst, vd, vn, vm);
767 } else {
768 return new VpmaxDFp<float>(machInst, vd, vn, vm);
769 }
770 } else {
771 if (q) {
772 return new VpminQFp<float>(machInst, vd, vn, vm);
773 } else {
774 return new VpminDFp<float>(machInst, vd, vn, vm);
775 }
776 }
777 } else {
778 if (bits(c, 1) == 0) {
779 if (q) {
780 return new VmaxQFp<float>(machInst, vd, vn, vm);
781 } else {
782 return new VmaxDFp<float>(machInst, vd, vn, vm);
783 }
784 } else {
785 if (q) {
786 return new VminQFp<float>(machInst, vd, vn, vm);

--- 111 unchanged lines hidden (view full) ---

898 }
899 }
900 return new Unknown(machInst);
901 }
902
903 static StaticInstPtr
904 decodeNeonTwoRegAndShift(ExtMachInst machInst)
905 {
906 const uint32_t a = bits(machInst, 11, 8);
907 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
908 const bool b = bits(machInst, 6);
909 const bool l = bits(machInst, 7);
910 const IntRegIndex vd =
911 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
912 (bits(machInst, 22) << 4)));
913 const IntRegIndex vm =
914 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
915 (bits(machInst, 5) << 4)));
916 unsigned imm6 = bits(machInst, 21, 16);

--- 5 unchanged lines hidden (view full) ---

922 if (bitSel & imm)
923 break;
924 else if (!size)
925 return new Unknown(machInst);
926 size--;
927 }
928 lShiftAmt = imm6 & ~bitSel;
929 unsigned rShiftAmt = 0;
930 if (a != 0xe && a != 0xf) {
931 if (size > 2)
932 rShiftAmt = 64 - imm6;
933 else
934 rShiftAmt = 2 * (8 << size) - imm6;
935 }
936
937 switch (a) {
938 case 0x0:
939 return decodeNeonUSTwoShiftReg<NVshrD, NVshrQ>(
940 b, u, size, machInst, vd, vm, rShiftAmt);
941 case 0x1:
942 return decodeNeonUSTwoShiftReg<NVsraD, NVsraQ>(
943 b, u, size, machInst, vd, vm, rShiftAmt);
944 case 0x2:
945 return decodeNeonUSTwoShiftReg<NVrshrD, NVrshrQ>(
946 b, u, size, machInst, vd, vm, rShiftAmt);
947 case 0x3:
948 return decodeNeonUSTwoShiftReg<NVrsraD, NVrsraQ>(
949 b, u, size, machInst, vd, vm, rShiftAmt);
950 case 0x4:
951 if (u) {
952 return decodeNeonUTwoShiftReg<NVsriD, NVsriQ>(
953 b, size, machInst, vd, vm, rShiftAmt);
954 } else {
955 return new Unknown(machInst);
956 }
957 case 0x5:
958 if (u) {
959 return decodeNeonUTwoShiftReg<NVsliD, NVsliQ>(
960 b, size, machInst, vd, vm, lShiftAmt);
961 } else {
962 return decodeNeonUTwoShiftReg<NVshlD, NVshlQ>(
963 b, size, machInst, vd, vm, lShiftAmt);
964 }
965 case 0x6:
966 case 0x7:
967 if (u) {
968 if (a == 0x6) {
969 return decodeNeonSTwoShiftReg<NVqshlusD, NVqshlusQ>(
970 b, size, machInst, vd, vm, lShiftAmt);
971 } else {
972 return decodeNeonUTwoShiftReg<NVqshluD, NVqshluQ>(
973 b, size, machInst, vd, vm, lShiftAmt);
974 }
975 } else {
976 return decodeNeonSTwoShiftReg<NVqshlD, NVqshlQ>(
977 b, size, machInst, vd, vm, lShiftAmt);
978 }
979 case 0x8:
980 if (l) {
981 return new Unknown(machInst);
982 } else if (u) {
983 return decodeNeonSTwoShiftSReg<NVqshruns, NVqrshruns>(
984 b, size, machInst, vd, vm, rShiftAmt);
985 } else {
986 return decodeNeonUTwoShiftSReg<NVshrn, NVrshrn>(
987 b, size, machInst, vd, vm, rShiftAmt);
988 }
989 case 0x9:
990 if (l) {
991 return new Unknown(machInst);
992 } else if (u) {
993 return decodeNeonUTwoShiftSReg<NVqshrun, NVqrshrun>(
994 b, size, machInst, vd, vm, rShiftAmt);
995 } else {
996 return decodeNeonSTwoShiftSReg<NVqshrn, NVqrshrn>(
997 b, size, machInst, vd, vm, rShiftAmt);
998 }
999 case 0xa:
1000 if (l || b) {
1001 return new Unknown(machInst);
1002 } else {
1003 return decodeNeonUSTwoShiftSReg<NVmovl, NVshll>(
1004 lShiftAmt, u, size, machInst, vd, vm, lShiftAmt);
1005 }
1006 case 0xe:
1007 if (l) {
1008 return new Unknown(machInst);
1009 } else {
1010 if (bits(imm6, 5) == 0)
1011 return new Unknown(machInst);
1012 if (u) {
1013 if (b) {
1014 return new NVcvtu2fpQ<float>(
1015 machInst, vd, vm, 64 - imm6);
1016 } else {
1017 return new NVcvtu2fpD<float>(
1018 machInst, vd, vm, 64 - imm6);
1019 }
1020 } else {
1021 if (b) {
1022 return new NVcvts2fpQ<float>(
1023 machInst, vd, vm, 64 - imm6);
1024 } else {
1025 return new NVcvts2fpD<float>(
1026 machInst, vd, vm, 64 - imm6);
1027 }
1028 }
1029 }
1030 case 0xf:
1031 if (l) {
1032 return new Unknown(machInst);
1033 } else {
1034 if (bits(imm6, 5) == 0)
1035 return new Unknown(machInst);
1036 if (u) {
1037 if (b) {
1038 return new NVcvt2ufxQ<float>(
1039 machInst, vd, vm, 64 - imm6);
1040 } else {
1041 return new NVcvt2ufxD<float>(
1042 machInst, vd, vm, 64 - imm6);
1043 }
1044 } else {
1045 if (b) {
1046 return new NVcvt2sfxQ<float>(
1047 machInst, vd, vm, 64 - imm6);
1048 } else {
1049 return new NVcvt2sfxD<float>(
1050 machInst, vd, vm, 64 - imm6);
1051 }
1052 }
1053 }
1054 }
1055 return new Unknown(machInst);
1056 }
1057
1058 static StaticInstPtr
1059 decodeNeonThreeRegDiffLengths(ExtMachInst machInst)
1060 {
1061 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
1062 const uint32_t a = bits(machInst, 11, 8);
1063 const IntRegIndex vd =
1064 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
1065 (bits(machInst, 22) << 4)));
1066 const IntRegIndex vn =
1067 (IntRegIndex)(2 * (bits(machInst, 19, 16) |
1068 (bits(machInst, 7) << 4)));
1069 const IntRegIndex vm =
1070 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
1071 (bits(machInst, 5) << 4)));
1072 const unsigned size = bits(machInst, 21, 20);
1073 switch (a) {
1074 case 0x0:
1075 return decodeNeonUSThreeUSReg<Vaddl>(
1076 u, size, machInst, vd, vn, vm);
1077 case 0x1:
1078 return decodeNeonUSThreeUSReg<Vaddw>(
1079 u, size, machInst, vd, vn, vm);
1080 case 0x2:
1081 return decodeNeonUSThreeUSReg<Vsubl>(

--- 64 unchanged lines hidden (view full) ---

1146 }
1147 return new Unknown(machInst);
1148 }
1149
1150 static StaticInstPtr
1151 decodeNeonTwoRegScalar(ExtMachInst machInst)
1152 {
1153 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
1154 const uint32_t a = bits(machInst, 11, 8);
1155 const unsigned size = bits(machInst, 21, 20);
1156 const IntRegIndex vd =
1157 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
1158 (bits(machInst, 22) << 4)));
1159 const IntRegIndex vn =
1160 (IntRegIndex)(2 * (bits(machInst, 19, 16) |
1161 (bits(machInst, 7) << 4)));
1162 const IntRegIndex vm = (size == 2) ?
1163 (IntRegIndex)(2 * bits(machInst, 3, 0)) :
1164 (IntRegIndex)(2 * bits(machInst, 2, 0));
1165 const unsigned index = (size == 2) ? (unsigned)bits(machInst, 5) :
1166 (bits(machInst, 3) | (bits(machInst, 5) << 1));
1167 switch (a) {
1168 case 0x0:
1169 if (u) {
1170 switch (size) {
1171 case 1:
1172 return new VmlasQ<uint16_t>(machInst, vd, vn, vm, index);
1173 case 2:
1174 return new VmlasQ<uint32_t>(machInst, vd, vn, vm, index);
1175 default:

--- 228 unchanged lines hidden (view full) ---

1404 }
1405 }
1406 return new Unknown(machInst);
1407 }
1408
1409 static StaticInstPtr
1410 decodeNeonTwoRegMisc(ExtMachInst machInst)
1411 {
1412 const uint32_t a = bits(machInst, 17, 16);
1413 const uint32_t b = bits(machInst, 10, 6);
1414 const bool q = bits(machInst, 6);
1415 const IntRegIndex vd =
1416 (IntRegIndex)(2 * (bits(machInst, 15, 12) |
1417 (bits(machInst, 22) << 4)));
1418 const IntRegIndex vm =
1419 (IntRegIndex)(2 * (bits(machInst, 3, 0) |
1420 (bits(machInst, 5) << 4)));
1421 const unsigned size = bits(machInst, 19, 18);
1422 switch (a) {
1423 case 0x0:
1424 switch (bits(b, 4, 1)) {
1425 case 0x0:
1426 switch (size) {
1427 case 0:
1428 if (q) {
1429 return new NVrev64Q<uint8_t>(machInst, vd, vm);
1430 } else {

--- 311 unchanged lines hidden (view full) ---

1742 return new Unknown(machInst);
1743 }
1744
1745 StaticInstPtr
1746 decodeNeonData(ExtMachInst machInst)
1747 {
1748 const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
1749 const uint32_t a = bits(machInst, 23, 19);
1750 const uint32_t b = bits(machInst, 11, 8);
1751 const uint32_t c = bits(machInst, 7, 4);
1752 if (bits(a, 4) == 0) {
1753 return decodeNeonThreeRegistersSameLength(machInst);
1754 } else if ((c & 0x9) == 1) {
1755 if ((a & 0x7) == 0) {
1756 return decodeNeonOneRegModImm(machInst);
1757 } else {
1758 return decodeNeonTwoRegAndShift(machInst);

--- 23 unchanged lines hidden (view full) ---

1782 if (imm4 >= 16 && !q)
1783 return new Unknown(machInst);
1784 if (q) {
1785 return new NVextQ<uint8_t>(machInst, vd, vn, vm, imm4);
1786 } else {
1787 return new NVextD<uint8_t>(machInst, vd, vn, vm, imm4);
1788 }
1789 }
1790 } else if (bits(b, 3) == 0 && bits(c, 0) == 0) {
1791 return decodeNeonTwoRegMisc(machInst);
1792 } else if (bits(b, 3, 2) == 0x2 && bits(c, 0) == 0) {
1793 unsigned length = bits(machInst, 9, 8) + 1;
1794 if ((uint32_t)vn / 2 + length > 32)
1795 return new Unknown(machInst);
1796 if (bits(machInst, 6) == 0) {
1797 switch (length) {
1798 case 1:
1799 return new NVtbl1(machInst, vd, vn, vm);
1800 case 2:

--- 10 unchanged lines hidden (view full) ---

1811 case 2:
1812 return new NVtbx2(machInst, vd, vn, vm);
1813 case 3:
1814 return new NVtbx3(machInst, vd, vn, vm);
1815 case 4:
1816 return new NVtbx4(machInst, vd, vn, vm);
1817 }
1818 }
1819 } else if (b == 0xc && (c & 0x9) == 0) {
1820 unsigned imm4 = bits(machInst, 19, 16);
1821 if (bits(imm4, 2, 0) == 0)
1822 return new Unknown(machInst);
1823 unsigned size = 0;
1824 while ((imm4 & 0x1) == 0) {
1825 size++;
1826 imm4 >>= 1;
1827 }

--- 194 unchanged lines hidden (view full) ---

2022 }
2023 }
2024 StaticInstPtr
2025 decodeShortFpTransfer(ExtMachInst machInst)
2026 {
2027 const uint32_t l = bits(machInst, 20);
2028 const uint32_t c = bits(machInst, 8);
2029 const uint32_t a = bits(machInst, 23, 21);
2030 const uint32_t b = bits(machInst, 6, 5);
2031 const uint32_t o1 = bits(machInst, 18);
2032 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
2033 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
2034 // Determine if this is backported aarch64 FP instruction
2035 const bool b31_b24 = bits(machInst, 31, 24) == 0xFE;
2036 const bool b23 = bits(machInst, 23);
2037 const bool b21_b19 = bits(machInst, 21, 19) == 0x7;
2038 const bool b11_b9 = bits(machInst, 11, 9) == 0x5;

--- 213 unchanged lines hidden (view full) ---

2252 } else if (bits(machInst, 5) == 1) {
2253 return new VmovCoreRegH(machInst, (IntRegIndex)vd,
2254 rt, bits(machInst, 6));
2255 } else if (bits(machInst, 6) == 0) {
2256 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
2257 } else {
2258 return new Unknown(machInst);
2259 }
2260 } else if (bits(b, 1) == 0) {
2261 bool q = bits(machInst, 21);
2262 unsigned be = (bits(machInst, 22) << 1) | (bits(machInst, 5));
2263 IntRegIndex vd = (IntRegIndex)(2 * (uint32_t)
2264 (bits(machInst, 19, 16) | (bits(machInst, 7) << 4)));
2265 IntRegIndex rt = (IntRegIndex)(uint32_t)
2266 bits(machInst, 15, 12);
2267 if (q) {
2268 switch (be) {

--- 533 unchanged lines hidden ---