1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2016-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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1996}};
1997
1998let {{
1999 header_output = '''
2000 StaticInstPtr
2001 decodeShortFpTransfer(ExtMachInst machInst);
2002 '''
2003 decoder_output = '''
2004 StaticInstPtr
2005 decodeShortFpTransfer(ExtMachInst machInst)
2006 {
2007 const uint32_t l = bits(machInst, 20);
2008 const uint32_t c = bits(machInst, 8);
2009 const uint32_t a = bits(machInst, 23, 21);
2010 const uint32_t b = bits(machInst, 6, 5);
2011 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
2012 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
2013 // Determine if this is backported aarch64 FP instruction
2014 const bool b31_b24 = bits(machInst, 31, 24) == 0xFE;
2015 const bool b23 = bits(machInst, 23);
2016 const bool b21_b18 = bits(machInst, 21, 18) == 0xE;
2017 const bool b11_b9 = bits(machInst, 11, 9) == 0x5;
2018 const bool sz = bits(machInst, 8);
2019 const bool b7_b6 = bits(machInst, 7, 6) == 0x1;
2020 const bool b6 = bits(machInst, 6) == 0x0;
2021 const bool b4 = bits(machInst, 4) == 0x0;
2022 if (b31_b24 && b23 && b21_b18 && b11_b9 && b7_b6 && b4) {
2023 // VINT* Integer Rounding Instructon
2024 const uint32_t rm = bits(machInst, 17, 16);
2025
2026 if (sz) {
2027 const IntRegIndex vd =
2028 (IntRegIndex)((bits(machInst, 22) << 5) |
2029 (bits(machInst, 15, 12) << 1));
2030 const IntRegIndex vm =
2031 (IntRegIndex)((bits(machInst, 5) << 5) |
2032 (bits(machInst, 3, 0) << 1));
2033 switch(rm) {
2034 case 0x0:
2035 return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm,
2036 true);
2037 case 0x1:
2038 return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm,
2039 true);
2040 case 0x2:
2041 return decodeVfpRegRegOp<VRIntPD>(machInst, vd, vm,
2042 true);
2043 case 0x3:
2044 return decodeVfpRegRegOp<VRIntMD>(machInst, vd, vm,
2045 true);
2046 default: return new Unknown(machInst);
2047 }
2048 } else {
2049 const IntRegIndex vd =
2050 (IntRegIndex)(bits(machInst, 22) |
2051 (bits(machInst, 15, 12) << 1));
2052 const IntRegIndex vm =
2053 (IntRegIndex)(bits(machInst, 5) |
2054 (bits(machInst, 3, 0) << 1));
2055 switch(rm) {
2056 case 0x0:
2057 return decodeVfpRegRegOp<VRIntAS>(machInst, vd, vm,
2058 false);
2059 case 0x1:
2060 return decodeVfpRegRegOp<VRIntNS>(machInst, vd, vm,
2061 false);
2062 case 0x2:
2063 return decodeVfpRegRegOp<VRIntPS>(machInst, vd, vm,
2064 false);
2065 case 0x3:
2066 return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm,
2067 false);
2068 default: return new Unknown(machInst);
2069 }
2070 }
2071 } else if (b31_b24 && !b23 && b11_b9 && b6 && b4){
2072 // VSEL* floating point conditional select
2073
2074 ConditionCode cond;
2075 switch(bits(machInst, 21, 20)) {
2076 case 0x0: cond = COND_EQ; break;
2077 case 0x1: cond = COND_VS; break;
2078 case 0x2: cond = COND_GE; break;
2079 case 0x3: cond = COND_GT; break;
2080 }
2081
2082 if (sz) {
2083 const IntRegIndex vd =
2084 (IntRegIndex)((bits(machInst, 22) << 5) |
2085 (bits(machInst, 15, 12) << 1));
2086 const IntRegIndex vm =
2087 (IntRegIndex)((bits(machInst, 5) << 5) |
2088 (bits(machInst, 3, 0) << 1));
2089 const IntRegIndex vn =
2090 (IntRegIndex)((bits(machInst, 7) << 5) |
2091 (bits(machInst, 19, 16) << 1));
2092 return new VselD(machInst, vd, vn, vm, cond);
2093 } else {
2094 const IntRegIndex vd =
2095 (IntRegIndex)(bits(machInst, 22) |
2096 (bits(machInst, 15, 12) << 1));
2097 const IntRegIndex vm =
2098 (IntRegIndex)(bits(machInst, 5) |
2099 (bits(machInst, 3, 0) << 1));
2100 const IntRegIndex vn =
2101 (IntRegIndex)((bits(machInst, 19, 16) << 1) |
2102 bits(machInst, 7));
2103 return new VselS(machInst, vd, vn, vm, cond);
2104 }
2105 } else {
2106 return new Unknown(machInst);
2107 }

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