1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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476 decoder_output = '''
477 StaticInstPtr
478 decodeVfpData(ExtMachInst machInst)
479 {
480 const uint32_t opc1 = bits(machInst, 23, 20);
481 const uint32_t opc2 = bits(machInst, 19, 16);
482 const uint32_t opc3 = bits(machInst, 7, 6);
483 //const uint32_t opc4 = bits(machInst, 3, 0);
484 const bool single = (bits(machInst, 8) == 0);
485 IntRegIndex vd;
486 IntRegIndex vm;
487 IntRegIndex vn;
488 if (single) {
489 vd = (IntRegIndex)(bits(machInst, 22) |
490 (bits(machInst, 15, 12) << 1));
491 vm = (IntRegIndex)(bits(machInst, 5) |
492 (bits(machInst, 3, 0) << 1));
493 vn = (IntRegIndex)(bits(machInst, 7) |
494 (bits(machInst, 19, 16) << 1));
495 } else {
496 vd = (IntRegIndex)((bits(machInst, 22) << 5) |
497 (bits(machInst, 15, 12) << 1));
498 vm = (IntRegIndex)((bits(machInst, 5) << 5) |
499 (bits(machInst, 3, 0) << 1));
500 vn = (IntRegIndex)((bits(machInst, 7) << 5) |
501 (bits(machInst, 19, 16) << 1));
502 }
503 switch (opc1 & 0xb /* 1011 */) {
504 case 0x0:
505 if (bits(machInst, 6) == 0) {
506 if (single) {
507 return new VmlaS(machInst, vd, vn, vm);
508 } else {
509 return new VmlaD(machInst, vd, vn, vm);
510 }
511 } else {
512 if (single) {
513 return new VmlsS(machInst, vd, vn, vm);
514 } else {
515 return new VmlsD(machInst, vd, vn, vm);
516 }
517 }
518 case 0x1:
519 if (bits(machInst, 6) == 1) {
520 if (single) {
521 return new VnmlaS(machInst, vd, vn, vm);
522 } else {
523 return new VnmlaD(machInst, vd, vn, vm);
524 }
525 } else {
526 if (single) {
527 return new VnmlsS(machInst, vd, vn, vm);
528 } else {
529 return new VnmlsD(machInst, vd, vn, vm);
530 }
531 }
532 case 0x2:
533 if ((opc3 & 0x1) == 0) {
534 if (single) {
535 return new VmulS(machInst, vd, vn, vm);
536 } else {
537 return new VmulD(machInst, vd, vn, vm);
538 }
539 } else {
540 if (single) {
541 return new VnmulS(machInst, vd, vn, vm);
542 } else {
543 return new VnmulD(machInst, vd, vn, vm);
544 }
545 }
546 case 0x3:
547 if ((opc3 & 0x1) == 0) {
548 if (single) {
549 return new VaddS(machInst, vd, vn, vm);
550 } else {
551 return new VaddD(machInst, vd, vn, vm);
552 }
553 } else {
554 if (single) {
555 return new VsubS(machInst, vd, vn, vm);
556 } else {
557 return new VsubD(machInst, vd, vn, vm);
558 }
559 }
560 case 0x8:
561 if ((opc3 & 0x1) == 0) {
562 if (single) {
563 return new VdivS(machInst, vd, vn, vm);
564 } else {
565 return new VdivD(machInst, vd, vn, vm);
566 }
567 }
568 break;
569 case 0xb:
570 if ((opc3 & 0x1) == 0) {
571 const uint32_t baseImm =
572 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
573 if (single) {
574 uint32_t imm = vfp_modified_imm(baseImm, false);
575 return new VmovImmS(machInst, vd, imm);
576 } else {
577 uint64_t imm = vfp_modified_imm(baseImm, true);
578 return new VmovImmD(machInst, vd, imm);
579 }
580 }
581 switch (opc2) {
582 case 0x0:
583 if (opc3 == 1) {
584 if (single) {
585 return new VmovRegS(machInst, vd, vm);
586 } else {
587 return new VmovRegD(machInst, vd, vm);
588 }
589 } else {
590 if (single) {
591 return new VabsS(machInst, vd, vm);
592 } else {
593 return new VabsD(machInst, vd, vm);
594 }
595 }
596 case 0x1:
597 if (opc3 == 1) {
598 if (single) {
599 return new VnegS(machInst, vd, vm);
600 } else {
601 return new VnegD(machInst, vd, vm);
602 }
603 } else {
604 if (single) {
605 return new VsqrtS(machInst, vd, vm);
606 } else {
607 return new VsqrtD(machInst, vd, vm);
608 }
609 }
610 case 0x2:
611 case 0x3:
612 // Between half and single precision.
613 return new WarnUnimplemented("vcvtb, vcvtt", machInst);
614 case 0x4:
615 case 0x5:

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