1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2011, 2016-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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2029 if (!isInt and size == 3) {
2030 return (IntRegIndex)((bits(machInst, 22) << 5) |
2031 (bits(machInst, 15, 12) << 1));
2032 } else {
2033 return (IntRegIndex)(bits(machInst, 22) |
2034 (bits(machInst, 15, 12) << 1));
2035 }
2036 }
2037
2038 IntRegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt)
2039 {
2040 if (!isInt and size == 3) {
2041 return (IntRegIndex)((bits(machInst, 5) << 5) |
2042 (bits(machInst, 3, 0) << 1));
2043 } else {
2044 return (IntRegIndex)(bits(machInst, 5) |
2045 (bits(machInst, 3, 0) << 1));
2046 }
2047 }
2048
2049 IntRegIndex decodeFpVn(ExtMachInst machInst, uint32_t size)
2050 {
2051 if (size == 3) {
2052 return (IntRegIndex)((bits(machInst, 7) << 5) |
2053 (bits(machInst, 19, 16) << 1));
2054 } else {
2055 return (IntRegIndex)(bits(machInst, 7) |
2056 (bits(machInst, 19, 16) << 1));
2057 }
2058 }
2059
2060 StaticInstPtr
2061 decodeFloatingPointDataProcessing(ExtMachInst machInst) {
2062 const uint32_t op0 = bits(machInst, 23, 20);
2063 const uint32_t op1 = bits(machInst, 19, 16);
2064 const uint32_t op2 = bits(machInst, 9, 8);
2065 const uint32_t op3 = bits(machInst, 6);
2066 const uint32_t rm = bits(machInst, 17, 16);
2067 const uint32_t size = bits(machInst, 9, 8);
2068 IntRegIndex vd = decodeFpVd(machInst, size, false);
2069 IntRegIndex vm = decodeFpVm(machInst, size, false);
2070 IntRegIndex vdInt = decodeFpVd(machInst, size, true);
2071 IntRegIndex vn = decodeFpVn(machInst, size);
2072 if (bits(machInst, 31, 24) == 0xFE && !bits(machInst, 4)) {
2073 if (bits(op0, 3) == 0 && op2 != 0 && !op3){
2074 ConditionCode cond;
2075 switch(bits(machInst, 21, 20)) {
2076 case 0x0: cond = COND_EQ; break;
2077 case 0x1: cond = COND_VS; break;
2078 case 0x2: cond = COND_GE; break;
2079 case 0x3: cond = COND_GT; break;
2080 }
2081 if (size == 3) {
2082 return new VselD(machInst, vd, vn, vm, cond);
2083 } else {
2084 return new VselS(machInst, vd, vn, vm, cond);
2085 }
2086 } else if (bits(op0, 3) == 1 && bits(op0, 1, 0) == 0 && op2 != 0) {
2087 const bool op = bits(machInst, 6);
2088 if (op) {
2089 if (size == 1) {
2090 return new FailUnimplemented("vminnm.f16", machInst);
2091 }
2092 return decodeNeonSizeSingleDouble<VminnmS, VminnmD>(
2093 size, machInst, vd, vn, vm);
2094 } else {
2095 if (size == 1) {
2096 return new FailUnimplemented("vmaxnm.f16", machInst);
2097 }
2098 return decodeNeonSizeSingleDouble<VmaxnmS, VmaxnmD>(
2099 size, machInst, vd, vn, vm);
2100 }
2101 } else if (bits(op0, 3) && bits(op0, 1, 0) == 3 &&
2102 bits(op1, 3) && op2 != 0 && op3)
2103 {
2104 const uint32_t o1 = bits(machInst, 18);
2105 if (o1 == 0) {
2106 if (size == 3) {
2107 switch(rm) {
2108 case 0x0:
2109 return decodeVfpRegRegOp<VRIntAD>(machInst, vd, vm,
2110 true);
2111 case 0x1:
2112 return decodeVfpRegRegOp<VRIntND>(machInst, vd, vm,
2113 true);

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2134 return decodeVfpRegRegOp<VRIntMS>(machInst, vd, vm,
2135 false);
2136 default: return new Unknown(machInst);
2137 }
2138 }
2139 } else {
2140 const bool op = bits(machInst, 7);
2141 switch(rm) {
2142 case 0x0:
2143 switch(size) {
2144 case 0x0:
2145 return new Unknown(machInst);
2146 case 0x1:
2147 return new FailUnimplemented(
2148 "vcvta.u32.f16", machInst);
2149 case 0x2:
2150 if (op) {
2151 return new VcvtaFpSIntS(machInst, vdInt, vm);
2152 } else {
2153 return new VcvtaFpUIntS(machInst, vdInt, vm);
2154 }
2155 case 0x3:
2156 if (op) {
2157 return new VcvtaFpSIntD(machInst, vdInt, vm);
2158 } else {
2159 return new VcvtaFpUIntD(machInst, vdInt, vm);
2160 }
2161 default: return new Unknown(machInst);
2162 }
2163 case 0x1:
2164 switch(size) {
2165 case 0x0:
2166 return new Unknown(machInst);
2167 case 0x1:
2168 return new FailUnimplemented(
2169 "vcvtn.u32.f16", machInst);
2170 case 0x2:
2171 if (op) {
2172 return new VcvtnFpSIntS(machInst, vdInt, vm);
2173 } else {
2174 return new VcvtnFpUIntS(machInst, vdInt, vm);
2175 }
2176 case 0x3:
2177 if (op) {
2178 return new VcvtnFpSIntD(machInst, vdInt, vm);
2179 } else {
2180 return new VcvtnFpUIntD(machInst, vdInt, vm);
2181 }
2182 default: return new Unknown(machInst);
2183 }
2184 case 0x2:
2185 switch(size) {
2186 case 0x0:
2187 return new Unknown(machInst);
2188 case 0x1:
2189 return new FailUnimplemented(
2190 "vcvtp.u32.f16", machInst);
2191 case 0x2:
2192 if (op) {
2193 return new VcvtpFpSIntS(machInst, vdInt, vm);
2194 } else {
2195 return new VcvtpFpUIntS(machInst, vdInt, vm);
2196 }
2197 case 0x3:
2198 if (op) {
2199 return new VcvtpFpSIntD(machInst, vdInt, vm);
2200 } else {
2201 return new VcvtpFpUIntD(machInst, vdInt, vm);
2202 }
2203 default: return new Unknown(machInst);
2204 }
2205 case 0x3:
2206 switch(size) {
2207 case 0x0:
2208 return new Unknown(machInst);
2209 case 0x1:
2210 return new FailUnimplemented(
2211 "vcvtm.u32.f16", machInst);
2212 case 0x2:
2213 if (op) {
2214 return new VcvtmFpSIntS(machInst, vdInt, vm);
2215 } else {
2216 return new VcvtmFpUIntS(machInst, vdInt, vm);
2217 }
2218 case 0x3:
2219 if (op) {
2220 return new VcvtmFpSIntD(machInst, vdInt, vm);
2221 } else {
2222 return new VcvtmFpUIntD(machInst, vdInt, vm);
2223 }
2224 default: return new Unknown(machInst);
2225 }
2226 default: return new Unknown(machInst);
2227 }
2228 }
2229 } else {
2230 return new Unknown(machInst);
2231 }
2232 } else {
2233 return new Unknown(machInst);
2234 }
2235 }
2236
2237 StaticInstPtr
2238 decodeShortFpTransfer(ExtMachInst machInst)
2239 {
2240 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
2241 (machInst.thumb == 0 && machInst.condCode == 0xf)) {
2242 return decodeFloatingPointDataProcessing(machInst);
2243 }
2244 const uint32_t l = bits(machInst, 20);
2245 const uint32_t c = bits(machInst, 8);
2246 const uint32_t a = bits(machInst, 23, 21);
2247 const uint32_t q = bits(machInst, 6, 5);
2248 if (l == 0 && c == 0) {
2249 if (a == 0) {
2250 const uint32_t vn = (bits(machInst, 19, 16) << 1) |
2251 bits(machInst, 7);
2252 const IntRegIndex rt =
2253 (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
2254 if (bits(machInst, 20) == 1) {
2255 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);

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