1// -*- mode:c++ -*-
2
3// Copyright (c) 2010,2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Breakpoint instructions
46//
47
48output header {{
49 /**
50 * Static instruction class for Breakpoint (illegal) instructions.
51 * These cause simulator termination if they are executed in a
52 * non-speculative mode. This is a leaf class.
53 */
54 class Breakpoint : public ArmStaticInst
55 {
56 public:
57 /// Constructor
58 Breakpoint(ExtMachInst _machInst)
59 : ArmStaticInst("Breakpoint", _machInst, No_OpClass)
60 {
61 // don't call execute() (which panics) if we're on a
62 // speculative path
63 flags[IsNonSpeculative] = true;
64 }
65
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010,2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Breakpoint instructions
46//
47
48output header {{
49 /**
50 * Static instruction class for Breakpoint (illegal) instructions.
51 * These cause simulator termination if they are executed in a
52 * non-speculative mode. This is a leaf class.
53 */
54 class Breakpoint : public ArmStaticInst
55 {
56 public:
57 /// Constructor
58 Breakpoint(ExtMachInst _machInst)
59 : ArmStaticInst("Breakpoint", _machInst, No_OpClass)
60 {
61 // don't call execute() (which panics) if we're on a
62 // speculative path
63 flags[IsNonSpeculative] = true;
64 }
65
|
70 };
71}};
72
73output decoder {{
74 std::string
75 Breakpoint::generateDisassembly(Addr pc, const SymbolTable *symtab) const
76 {
77 return csprintf("%-10s (inst 0x%x)", "Breakpoint", machInst);
78 }
79}};
80
81output exec {{
82 Fault
83 Breakpoint::execute(ExecContext *xc, Trace::InstRecord *traceData) const
84 {
85 return std::make_shared<PrefetchAbort>(xc->pcState().pc(),
86 ArmFault::DebugEvent);
87 }
88}};
89
90def format ArmBkptHlt() {{
91 decode_block = '''
92 {
93 if (bits(machInst, 21)) {
94 return new Breakpoint(machInst);
95 } else {
96 uint32_t imm16 = (bits(machInst, 19, 8) << 4) |
97 (bits(machInst, 3, 0) << 0);
98 return new Hlt(machInst, imm16);
99 }
100 }
101 '''
102}};
103
| 70 };
71}};
72
73output decoder {{
74 std::string
75 Breakpoint::generateDisassembly(Addr pc, const SymbolTable *symtab) const
76 {
77 return csprintf("%-10s (inst 0x%x)", "Breakpoint", machInst);
78 }
79}};
80
81output exec {{
82 Fault
83 Breakpoint::execute(ExecContext *xc, Trace::InstRecord *traceData) const
84 {
85 return std::make_shared<PrefetchAbort>(xc->pcState().pc(),
86 ArmFault::DebugEvent);
87 }
88}};
89
90def format ArmBkptHlt() {{
91 decode_block = '''
92 {
93 if (bits(machInst, 21)) {
94 return new Breakpoint(machInst);
95 } else {
96 uint32_t imm16 = (bits(machInst, 19, 8) << 4) |
97 (bits(machInst, 3, 0) << 0);
98 return new Hlt(machInst, imm16);
99 }
100 }
101 '''
102}};
103
|