branch.isa (7605:94b2f78894ca) branch.isa (7613:62159049ca81)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 152 unchanged lines hidden (view full) ---

161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
164 const bool enable = bits(machInst, 10, 9) == 0x2;
165 const uint32_t mods = bits(machInst, 8, 0) |
166 ((enable ? 1 : 0) << 9);
167 return new Cps(machInst, mods);
168 } else if ((op2 & 0xf0) == 0xf0) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 152 unchanged lines hidden (view full) ---

161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
164 const bool enable = bits(machInst, 10, 9) == 0x2;
165 const uint32_t mods = bits(machInst, 8, 0) |
166 ((enable ? 1 : 0) << 9);
167 return new Cps(machInst, mods);
168 } else if ((op2 & 0xf0) == 0xf0) {
169 return new WarnUnimplemented("dbg", machInst);
169 return new Dbg(machInst);
170 } else {
171 switch (op2) {
172 case 0x0:
173 return new NopInst(machInst);
174 case 0x1:
175 return new YieldInst(machInst);
176 case 0x2:
177 return new WfeInst(machInst);

--- 124 unchanged lines hidden --- 		170 } else {
171 switch (op2) {
172 case 0x0:
173 return new NopInst(machInst);
174 case 0x1:
175 return new YieldInst(machInst);
176 case 0x2:
177 return new WfeInst(machInst);

--- 124 unchanged lines hidden ---