branch.isa (7290:ea9189fbb84f) branch.isa (7316:bb190cb8ee69)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 147 unchanged lines hidden (view full) ---

156 const uint8_t byteMask = bits(machInst, 11, 8);
157 return new MsrSpsrReg(machInst, rn, byteMask);
158 }
159 case 0x3a:
160 {
161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 147 unchanged lines hidden (view full) ---

156 const uint8_t byteMask = bits(machInst, 11, 8);
157 return new MsrSpsrReg(machInst, rn, byteMask);
158 }
159 case 0x3a:
160 {
161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
164 return new WarnUnimplemented("cps", machInst);
164 const bool enable = bits(machInst, 10, 9) == 0x2;
165 const uint32_t mods = bits(machInst, 8, 0) |
166 ((enable ? 1 : 0) << 9);
167 return new Cps(machInst, mods);
165 } else if ((op2 & 0xf0) == 0xf0) {
166 return new WarnUnimplemented("dbg", machInst);
167 } else {
168 switch (op2) {
169 case 0x0:
170 return new NopInst(machInst);
171 case 0x1:
172 return new WarnUnimplemented("yield", machInst);

--- 102 unchanged lines hidden --- 		168 } else if ((op2 & 0xf0) == 0xf0) {
169 return new WarnUnimplemented("dbg", machInst);
170 } else {
171 switch (op2) {
172 case 0x0:
173 return new NopInst(machInst);
174 case 0x1:
175 return new WarnUnimplemented("yield", machInst);

--- 102 unchanged lines hidden ---