branch.isa (7248:f5563135de40) branch.isa (7252:bba68021edca)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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66 return new BlxImm(machInst, imm);
67 } else {
68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69 (ConditionCode)(uint32_t)machInst.condCode);
70 }
71 '''
72}};
73
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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66 return new BlxImm(machInst, imm);
67 } else {
68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69 (ConditionCode)(uint32_t)machInst.condCode);
70 }
71 '''
72}};
73
74def format ArmBx() {{
74def format ArmBxClz() {{
75 decode_block = '''
75 decode_block = '''
76 return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
77 (ConditionCode)(uint32_t)machInst.condCode);
76 {
77 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
78 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
79 if (OPCODE == 0x9) {
80 return new BxReg(machInst, rm,
81 (ConditionCode)(uint32_t)machInst.condCode);
82 } else if (OPCODE == 0xb) {
83 return new Clz(machInst, rd, rm);
84 } else {
85 return new Unknown(machInst);
86 }
87 }
78 '''
79}};
80
81def format ArmBlxReg() {{
82 decode_block = '''
83 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
84 (ConditionCode)(uint32_t)machInst.condCode);
85 '''

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88 '''
89}};
90
91def format ArmBlxReg() {{
92 decode_block = '''
93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
94 (ConditionCode)(uint32_t)machInst.condCode);
95 '''

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