branch.isa (7200:64bc968a1d10) branch.isa (7204:8ed494406e30)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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105 '''
106}};
107
108def format Thumb32BranchesAndMiscCtrl() {{
109 decode_block = '''
110 {
111 const uint32_t op = bits(machInst, 26, 20);
112 const uint32_t op1 = bits(machInst, 14, 12);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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105 '''
106}};
107
108def format Thumb32BranchesAndMiscCtrl() {{
109 decode_block = '''
110 {
111 const uint32_t op = bits(machInst, 26, 20);
112 const uint32_t op1 = bits(machInst, 14, 12);
113 const uint32_t op2 = bits(machInst, 11, 8);
114 switch (op1 & 0x5) {
115 case 0x0:
116 if (op == 127) {
117 if (op1 & 0x2) {
118 // Permanentl undefined.
119 return new WarnUnimplemented("undefined", machInst);
120 } else {
121 return new WarnUnimplemented("smc", machInst);

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129 const int32_t imm = sext<21>((s << 20) |
130 (j2 << 19) | (j1 << 18) |
131 (imm6 << 12) | (imm11 << 1));
132 return new B(machInst, imm,
133 (ConditionCode)(uint32_t)bits(machInst, 25, 22));
134 } else {
135 switch (op) {
136 case 0x38:
113 switch (op1 & 0x5) {
114 case 0x0:
115 if (op == 127) {
116 if (op1 & 0x2) {
117 // Permanentl undefined.
118 return new WarnUnimplemented("undefined", machInst);
119 } else {
120 return new WarnUnimplemented("smc", machInst);

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128 const int32_t imm = sext<21>((s << 20) |
129 (j2 << 19) | (j1 << 18) |
130 (imm6 << 12) | (imm11 << 1));
131 return new B(machInst, imm,
132 (ConditionCode)(uint32_t)bits(machInst, 25, 22));
133 } else {
134 switch (op) {
135 case 0x38:
137 if ((op2 & 0x3) == 0) {
138 // Application level
139 return new WarnUnimplemented("msr", machInst);
136 {
137 const IntRegIndex rn =
138 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
139 const uint8_t byteMask = bits(machInst, 11, 8);
140 return new MsrCpsrReg(machInst, rn, byteMask);
140 }
141 }
141 // Fall through on purpose...
142 case 0x39:
142 case 0x39:
143 // System level
144 return new WarnUnimplemented("msr", machInst);
143 {
144 const IntRegIndex rn =
145 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
146 const uint8_t byteMask = bits(machInst, 11, 8);
147 return new MsrSpsrReg(machInst, rn, byteMask);
148 }
145 case 0x3a:
146 {
147 const uint32_t op1 = bits(machInst, 10, 8);
148 const uint32_t op2 = bits(machInst, 7, 0);
149 if (op1 != 0) {
150 return new WarnUnimplemented("cps", machInst);
151 } else if ((op2 & 0xf0) == 0xf0) {
152 return new WarnUnimplemented("dbg", machInst);

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193 return new WarnUnimplemented("bxj", machInst);
194 case 0x3d:
195 {
196 const uint32_t imm32 = bits(machInst, 7, 0);
197 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
198 imm32, false);
199 }
200 case 0x3e:
149 case 0x3a:
150 {
151 const uint32_t op1 = bits(machInst, 10, 8);
152 const uint32_t op2 = bits(machInst, 7, 0);
153 if (op1 != 0) {
154 return new WarnUnimplemented("cps", machInst);
155 } else if ((op2 & 0xf0) == 0xf0) {
156 return new WarnUnimplemented("dbg", machInst);

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197 return new WarnUnimplemented("bxj", machInst);
198 case 0x3d:
199 {
200 const uint32_t imm32 = bits(machInst, 7, 0);
201 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
202 imm32, false);
203 }
204 case 0x3e:
205 {
206 const IntRegIndex rd =
207 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
208 return new MrsCpsr(machInst, rd);
209 }
201 case 0x3f:
210 case 0x3f:
202 return new WarnUnimplemented("mrs", machInst);
211 {
212 const IntRegIndex rd =
213 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
214 return new MrsSpsr(machInst, rd);
215 }
203 }
204 break;
205 }
206 case 0x1:
207 {
208 const uint32_t s = bits(machInst, 26);
209 const uint32_t i1 = !(bits(machInst, 13) ^ s);
210 const uint32_t i2 = !(bits(machInst, 11) ^ s);

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217 break;
218 }
219 case 0x1:
220 {
221 const uint32_t s = bits(machInst, 26);
222 const uint32_t i1 = !(bits(machInst, 13) ^ s);
223 const uint32_t i2 = !(bits(machInst, 11) ^ s);

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