branch.isa (7144:097e00bcf084) branch.isa (7152:a1308654b445)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright

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28//
29// Authors: Stephen Hines
30
31////////////////////////////////////////////////////////////////////
32//
33// Control transfer instructions
34//
35
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright

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40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Control transfer instructions
46//
47
48def format ArmBBlxImm() {{
49 decode_block = '''
50 if (machInst.condCode == 0xF) {
51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
52 (bits(machInst, 24) << 1);
53 return new BlxImm(machInst, imm);
54 } else {
55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
56 (ConditionCode)(uint32_t)machInst.condCode);
57 }
58 '''
59}};
60
61def format ArmBlBlxImm() {{
62 decode_block = '''
63 if (machInst.condCode == 0xF) {
64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
65 (bits(machInst, 24) << 1);
66 return new BlxImm(machInst, imm);
67 } else {
68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69 (ConditionCode)(uint32_t)machInst.condCode);
70 }
71 '''
72}};
73
74def format ArmBx() {{
75 decode_block = '''
76 return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
77 (ConditionCode)(uint32_t)machInst.condCode);
78 '''
79}};
80
81def format ArmBlxReg() {{
82 decode_block = '''
83 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
84 (ConditionCode)(uint32_t)machInst.condCode);
85 '''
86}};
87
36def format Branch(code,*opt_flags) {{
37
38 #Build Instruction Flags
39 #Use Link & Likely Flags to Add Link/Condition Code
40 inst_flags = ('IsDirectControl', )
41 linking = False
42 for x in opt_flags:
43 if x == 'Link':

--- 67 unchanged lines hidden --- 		88def format Branch(code,*opt_flags) {{
89
90 #Build Instruction Flags
91 #Use Link & Likely Flags to Add Link/Condition Code
92 inst_flags = ('IsDirectControl', )
93 linking = False
94 for x in opt_flags:
95 if x == 'Link':

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