branch.isa (12248:858685d552f6) branch.isa (13354:c1bdac713ae5)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010,2012-2013,2017 ARM Limited
3// Copyright (c) 2010,2012-2013,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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160 } else {
161 return new MsrCpsrReg(machInst, rn, byteMask);
162 }
163 }
164 }
165 case 0x3a:
166 {
167 const uint32_t op1 = bits(machInst, 10, 8);
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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160 } else {
161 return new MsrCpsrReg(machInst, rn, byteMask);
162 }
163 }
164 }
165 case 0x3a:
166 {
167 const uint32_t op1 = bits(machInst, 10, 8);
168 const uint32_t op2 = bits(machInst, 7, 0);
168 const uint32_t hint = bits(machInst, 7, 4);
169 const uint32_t option = bits(machInst, 3, 0);
169 if (op1 != 0) {
170 const bool enable = bits(machInst, 10, 9) == 0x2;
171 const uint32_t mods = bits(machInst, 8, 0) |
172 ((enable ? 1 : 0) << 9);
173 return new Cps(machInst, mods);
170 if (op1 != 0) {
171 const bool enable = bits(machInst, 10, 9) == 0x2;
172 const uint32_t mods = bits(machInst, 8, 0) |
173 ((enable ? 1 : 0) << 9);
174 return new Cps(machInst, mods);
174 } else if ((op2 & 0xf0) == 0xf0) {
175 } else if (hint == 0xf) {
175 return new Dbg(machInst);
176 } else {
176 return new Dbg(machInst);
177 } else {
177 switch (op2) {
178 switch (hint) {
178 case 0x0:
179 case 0x0:
179 return new NopInst(machInst);
180 switch (option) {
181 case 0x0:
182 return new NopInst(machInst);
183 case 0x1:
184 return new YieldInst(machInst);
185 case 0x2:
186 return new WfeInst(machInst);
187 case 0x3:
188 return new WfiInst(machInst);
189 case 0x4:
190 return new SevInst(machInst);
191 case 0x5:
192 return new WarnUnimplemented(
193 "sevl", machInst);
194 }
195 break;
180 case 0x1:
196 case 0x1:
181 return new YieldInst(machInst);
182 case 0x2:
183 return new WfeInst(machInst);
184 case 0x3:
185 return new WfiInst(machInst);
186 case 0x4:
187 return new SevInst(machInst);
188 default:
197 switch (option) {
198 case 0x0:
199 return new WarnUnimplemented(
200 "esb", machInst);
201 case 0x2:
202 return new WarnUnimplemented(
203 "tsb csync", machInst);
204 case 0x4:
205 return new WarnUnimplemented(
206 "csdb", machInst);
207 }
189 break;
190 }
191 }
208 break;
209 }
210 }
192 break;
211 return new WarnUnimplemented(
212 "unallocated_hint", machInst);
193 }
194 case 0x3b:
195 {
196 const uint32_t op = bits(machInst, 7, 4);
197 switch (op) {
198 case 0x0:
199 return new Leavex(machInst);
200 case 0x1:

--- 104 unchanged lines hidden --- 		213 }
214 case 0x3b:
215 {
216 const uint32_t op = bits(machInst, 7, 4);
217 switch (op) {
218 case 0x0:
219 return new Leavex(machInst);
220 case 0x1:

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