1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Control transfer instructions
46//
47
48def format ArmBBlxImm() {{
49 decode_block = '''
50 if (machInst.condCode == 0xF) {
51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
52 (bits(machInst, 24) << 1);
53 return new BlxImm(machInst, imm);
54 } else {
55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
56 (ConditionCode)(uint32_t)machInst.condCode);
57 }
58 '''
59}};
60
61def format ArmBlBlxImm() {{
62 decode_block = '''
63 if (machInst.condCode == 0xF) {
64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
65 (bits(machInst, 24) << 1);
66 return new BlxImm(machInst, imm);
67 } else {
68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69 (ConditionCode)(uint32_t)machInst.condCode);
70 }
71 '''
72}};
73
74def format ArmBxClz() {{
75 decode_block = '''
76 {
77 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
78 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
79 if (OPCODE == 0x9) {
80 return new BxReg(machInst, rm,
81 (ConditionCode)(uint32_t)machInst.condCode);
82 } else if (OPCODE == 0xb) {
83 return new Clz(machInst, rd, rm);
84 } else {
85 return new Unknown(machInst);
86 }
87 }
88 '''
89}};
90
91def format ArmBlxReg() {{
92 decode_block = '''
93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
94 (ConditionCode)(uint32_t)machInst.condCode);
95 '''
96}};
97
98def format Thumb16CondBranchAndSvc() {{
99 decode_block = '''
100 if (bits(machInst, 11, 9) != 0x7) {
101 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1),
102 (ConditionCode)(uint32_t)bits(machInst, 11, 8));
103 } else if (bits(machInst, 8)) {
104 return new Svc(machInst);
105 } else {
106 // This space will not be allocated in the future.
107 return new Unknown(machInst);
108 }
109 '''
110}};
111
112def format Thumb16UncondBranch() {{
113 decode_block = '''
114 return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC);
115 '''
116}};
117
118def format Thumb32BranchesAndMiscCtrl() {{
119 decode_block = '''
120 {
121 const uint32_t op = bits(machInst, 26, 20);
122 const uint32_t op1 = bits(machInst, 14, 12);
123 switch (op1 & 0x5) {
124 case 0x0:
125 if (op == 127) {
126 if (op1 & 0x2) {
127 // Permanently undefined.
128 return new Unknown(machInst);
129 } else {
130 return new WarnUnimplemented("smc", machInst);
131 }
132 } else if ((op & 0x38) != 0x38) {
133 const uint32_t s = bits(machInst, 26);
134 const uint32_t j1 = bits(machInst, 13);
135 const uint32_t j2 = bits(machInst, 11);
136 const uint32_t imm6 = bits(machInst, 21, 16);
137 const uint32_t imm11 = bits(machInst, 10, 0);
138 const int32_t imm = sext<21>((s << 20) |
139 (j2 << 19) | (j1 << 18) |
140 (imm6 << 12) | (imm11 << 1));
141 return new B(machInst, imm,
142 (ConditionCode)(uint32_t)bits(machInst, 25, 22));
143 } else {
144 switch (op) {
145 case 0x38:
146 {
147 const IntRegIndex rn =
148 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
149 const uint8_t byteMask = bits(machInst, 11, 8);
150 return new MsrCpsrReg(machInst, rn, byteMask);
151 }
152 case 0x39:
153 {
154 const IntRegIndex rn =
155 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
156 const uint8_t byteMask = bits(machInst, 11, 8);
157 return new MsrSpsrReg(machInst, rn, byteMask);
158 }
159 case 0x3a:
160 {
161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
164 const bool enable = bits(machInst, 10, 9) == 0x2;
165 const uint32_t mods = bits(machInst, 8, 0) |
166 ((enable ? 1 : 0) << 9);
167 return new Cps(machInst, mods);
168 } else if ((op2 & 0xf0) == 0xf0) {
169 return new WarnUnimplemented("dbg", machInst);
170 } else {
171 switch (op2) {
172 case 0x0:
173 return new NopInst(machInst);
174 case 0x1:
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Control transfer instructions
46//
47
48def format ArmBBlxImm() {{
49 decode_block = '''
50 if (machInst.condCode == 0xF) {
51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
52 (bits(machInst, 24) << 1);
53 return new BlxImm(machInst, imm);
54 } else {
55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
56 (ConditionCode)(uint32_t)machInst.condCode);
57 }
58 '''
59}};
60
61def format ArmBlBlxImm() {{
62 decode_block = '''
63 if (machInst.condCode == 0xF) {
64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
65 (bits(machInst, 24) << 1);
66 return new BlxImm(machInst, imm);
67 } else {
68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69 (ConditionCode)(uint32_t)machInst.condCode);
70 }
71 '''
72}};
73
74def format ArmBxClz() {{
75 decode_block = '''
76 {
77 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
78 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
79 if (OPCODE == 0x9) {
80 return new BxReg(machInst, rm,
81 (ConditionCode)(uint32_t)machInst.condCode);
82 } else if (OPCODE == 0xb) {
83 return new Clz(machInst, rd, rm);
84 } else {
85 return new Unknown(machInst);
86 }
87 }
88 '''
89}};
90
91def format ArmBlxReg() {{
92 decode_block = '''
93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
94 (ConditionCode)(uint32_t)machInst.condCode);
95 '''
96}};
97
98def format Thumb16CondBranchAndSvc() {{
99 decode_block = '''
100 if (bits(machInst, 11, 9) != 0x7) {
101 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1),
102 (ConditionCode)(uint32_t)bits(machInst, 11, 8));
103 } else if (bits(machInst, 8)) {
104 return new Svc(machInst);
105 } else {
106 // This space will not be allocated in the future.
107 return new Unknown(machInst);
108 }
109 '''
110}};
111
112def format Thumb16UncondBranch() {{
113 decode_block = '''
114 return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC);
115 '''
116}};
117
118def format Thumb32BranchesAndMiscCtrl() {{
119 decode_block = '''
120 {
121 const uint32_t op = bits(machInst, 26, 20);
122 const uint32_t op1 = bits(machInst, 14, 12);
123 switch (op1 & 0x5) {
124 case 0x0:
125 if (op == 127) {
126 if (op1 & 0x2) {
127 // Permanently undefined.
128 return new Unknown(machInst);
129 } else {
130 return new WarnUnimplemented("smc", machInst);
131 }
132 } else if ((op & 0x38) != 0x38) {
133 const uint32_t s = bits(machInst, 26);
134 const uint32_t j1 = bits(machInst, 13);
135 const uint32_t j2 = bits(machInst, 11);
136 const uint32_t imm6 = bits(machInst, 21, 16);
137 const uint32_t imm11 = bits(machInst, 10, 0);
138 const int32_t imm = sext<21>((s << 20) |
139 (j2 << 19) | (j1 << 18) |
140 (imm6 << 12) | (imm11 << 1));
141 return new B(machInst, imm,
142 (ConditionCode)(uint32_t)bits(machInst, 25, 22));
143 } else {
144 switch (op) {
145 case 0x38:
146 {
147 const IntRegIndex rn =
148 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
149 const uint8_t byteMask = bits(machInst, 11, 8);
150 return new MsrCpsrReg(machInst, rn, byteMask);
151 }
152 case 0x39:
153 {
154 const IntRegIndex rn =
155 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
156 const uint8_t byteMask = bits(machInst, 11, 8);
157 return new MsrSpsrReg(machInst, rn, byteMask);
158 }
159 case 0x3a:
160 {
161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
164 const bool enable = bits(machInst, 10, 9) == 0x2;
165 const uint32_t mods = bits(machInst, 8, 0) |
166 ((enable ? 1 : 0) << 9);
167 return new Cps(machInst, mods);
168 } else if ((op2 & 0xf0) == 0xf0) {
169 return new WarnUnimplemented("dbg", machInst);
170 } else {
171 switch (op2) {
172 case 0x0:
173 return new NopInst(machInst);
174 case 0x1:
|
182 default:
183 break;
184 }
185 }
186 break;
187 }
188 case 0x3b:
189 {
190 const uint32_t op = bits(machInst, 7, 4);
191 switch (op) {
192 case 0x0:
193 return new Leavex(machInst);
194 case 0x1:
195 return new Enterx(machInst);
196 case 0x2:
197 return new WarnUnimplemented("clrex", machInst);
198 case 0x4:
199 return new WarnUnimplemented("dsb", machInst);
200 case 0x5:
201 return new WarnUnimplemented("dmb", machInst);
202 case 0x6:
203 return new WarnUnimplemented("isb", machInst);
204 default:
205 break;
206 }
207 break;
208 }
209 case 0x3c:
210 {
211 // On systems that don't support bxj, bxj == bx
212 return new BxReg(machInst,
213 (IntRegIndex)(uint32_t)bits(machInst, 19, 16),
214 COND_UC);
215 }
216 case 0x3d:
217 {
218 const uint32_t imm32 = bits(machInst, 7, 0);
219 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
220 imm32, false);
221 }
222 case 0x3e:
223 {
224 const IntRegIndex rd =
225 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
226 return new MrsCpsr(machInst, rd);
227 }
228 case 0x3f:
229 {
230 const IntRegIndex rd =
231 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
232 return new MrsSpsr(machInst, rd);
233 }
234 }
235 break;
236 }
237 case 0x1:
238 {
239 const uint32_t s = bits(machInst, 26);
240 const uint32_t i1 = !(bits(machInst, 13) ^ s);
241 const uint32_t i2 = !(bits(machInst, 11) ^ s);
242 const uint32_t imm10 = bits(machInst, 25, 16);
243 const uint32_t imm11 = bits(machInst, 10, 0);
244 const int32_t imm = sext<25>((s << 24) |
245 (i1 << 23) | (i2 << 22) |
246 (imm10 << 12) | (imm11 << 1));
247 return new B(machInst, imm, COND_UC);
248 }
249 case 0x4:
250 {
251 if (bits(machInst, 0) == 1) {
252 return new Unknown(machInst);
253 }
254 const uint32_t s = bits(machInst, 26);
255 const uint32_t i1 = !(bits(machInst, 13) ^ s);
256 const uint32_t i2 = !(bits(machInst, 11) ^ s);
257 const uint32_t imm10h = bits(machInst, 25, 16);
258 const uint32_t imm10l = bits(machInst, 10, 1);
259 const int32_t imm = sext<25>((s << 24) |
260 (i1 << 23) | (i2 << 22) |
261 (imm10h << 12) | (imm10l << 2));
262 return new BlxImm(machInst, imm);
263 }
264 case 0x5:
265 {
266 const uint32_t s = bits(machInst, 26);
267 const uint32_t i1 = !(bits(machInst, 13) ^ s);
268 const uint32_t i2 = !(bits(machInst, 11) ^ s);
269 const uint32_t imm10 = bits(machInst, 25, 16);
270 const uint32_t imm11 = bits(machInst, 10, 0);
271 const int32_t imm = sext<25>((s << 24) |
272 (i1 << 23) | (i2 << 22) |
273 (imm10 << 12) | (imm11 << 1));
274 return new Bl(machInst, imm, COND_UC);
275 }
276 default:
277 break;
278 }
279 return new Unknown(machInst);
280 }
281 '''
282}};
| 182 default:
183 break;
184 }
185 }
186 break;
187 }
188 case 0x3b:
189 {
190 const uint32_t op = bits(machInst, 7, 4);
191 switch (op) {
192 case 0x0:
193 return new Leavex(machInst);
194 case 0x1:
195 return new Enterx(machInst);
196 case 0x2:
197 return new WarnUnimplemented("clrex", machInst);
198 case 0x4:
199 return new WarnUnimplemented("dsb", machInst);
200 case 0x5:
201 return new WarnUnimplemented("dmb", machInst);
202 case 0x6:
203 return new WarnUnimplemented("isb", machInst);
204 default:
205 break;
206 }
207 break;
208 }
209 case 0x3c:
210 {
211 // On systems that don't support bxj, bxj == bx
212 return new BxReg(machInst,
213 (IntRegIndex)(uint32_t)bits(machInst, 19, 16),
214 COND_UC);
215 }
216 case 0x3d:
217 {
218 const uint32_t imm32 = bits(machInst, 7, 0);
219 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
220 imm32, false);
221 }
222 case 0x3e:
223 {
224 const IntRegIndex rd =
225 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
226 return new MrsCpsr(machInst, rd);
227 }
228 case 0x3f:
229 {
230 const IntRegIndex rd =
231 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
232 return new MrsSpsr(machInst, rd);
233 }
234 }
235 break;
236 }
237 case 0x1:
238 {
239 const uint32_t s = bits(machInst, 26);
240 const uint32_t i1 = !(bits(machInst, 13) ^ s);
241 const uint32_t i2 = !(bits(machInst, 11) ^ s);
242 const uint32_t imm10 = bits(machInst, 25, 16);
243 const uint32_t imm11 = bits(machInst, 10, 0);
244 const int32_t imm = sext<25>((s << 24) |
245 (i1 << 23) | (i2 << 22) |
246 (imm10 << 12) | (imm11 << 1));
247 return new B(machInst, imm, COND_UC);
248 }
249 case 0x4:
250 {
251 if (bits(machInst, 0) == 1) {
252 return new Unknown(machInst);
253 }
254 const uint32_t s = bits(machInst, 26);
255 const uint32_t i1 = !(bits(machInst, 13) ^ s);
256 const uint32_t i2 = !(bits(machInst, 11) ^ s);
257 const uint32_t imm10h = bits(machInst, 25, 16);
258 const uint32_t imm10l = bits(machInst, 10, 1);
259 const int32_t imm = sext<25>((s << 24) |
260 (i1 << 23) | (i2 << 22) |
261 (imm10h << 12) | (imm10l << 2));
262 return new BlxImm(machInst, imm);
263 }
264 case 0x5:
265 {
266 const uint32_t s = bits(machInst, 26);
267 const uint32_t i1 = !(bits(machInst, 13) ^ s);
268 const uint32_t i2 = !(bits(machInst, 11) ^ s);
269 const uint32_t imm10 = bits(machInst, 25, 16);
270 const uint32_t imm11 = bits(machInst, 10, 0);
271 const int32_t imm = sext<25>((s << 24) |
272 (i1 << 23) | (i2 << 22) |
273 (imm10 << 12) | (imm11 << 1));
274 return new Bl(machInst, imm, COND_UC);
275 }
276 default:
277 break;
278 }
279 return new Unknown(machInst);
280 }
281 '''
282}};
|