1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Control transfer instructions
46//
47
48def format ArmBBlxImm() {{
49 decode_block = '''
50 if (machInst.condCode == 0xF) {
51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
52 (bits(machInst, 24) << 1);
53 return new BlxImm(machInst, imm);
54 } else {
55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
56 (ConditionCode)(uint32_t)machInst.condCode);
57 }
58 '''
59}};
60
61def format ArmBlBlxImm() {{
62 decode_block = '''
63 if (machInst.condCode == 0xF) {
64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
65 (bits(machInst, 24) << 1);
66 return new BlxImm(machInst, imm);
67 } else {
68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69 (ConditionCode)(uint32_t)machInst.condCode);
70 }
71 '''
72}};
73
74def format ArmBxClz() {{
75 decode_block = '''
76 {
77 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
78 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
79 if (OPCODE == 0x9) {
80 return new BxReg(machInst, rm,
81 (ConditionCode)(uint32_t)machInst.condCode);
82 } else if (OPCODE == 0xb) {
83 return new Clz(machInst, rd, rm);
84 } else {
85 return new Unknown(machInst);
86 }
87 }
88 '''
89}};
90
91def format ArmBlxReg() {{
92 decode_block = '''
93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
94 (ConditionCode)(uint32_t)machInst.condCode);
95 '''
96}};
97
98def format Thumb16CondBranchAndSvc() {{
99 decode_block = '''
100 if (bits(machInst, 11, 9) != 0x7) {
101 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1),
102 (ConditionCode)(uint32_t)bits(machInst, 11, 8));
103 } else if (bits(machInst, 8)) {
104 return new Svc(machInst);
105 } else {
106 // This space will not be allocated in the future.
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Control transfer instructions
46//
47
48def format ArmBBlxImm() {{
49 decode_block = '''
50 if (machInst.condCode == 0xF) {
51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
52 (bits(machInst, 24) << 1);
53 return new BlxImm(machInst, imm);
54 } else {
55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
56 (ConditionCode)(uint32_t)machInst.condCode);
57 }
58 '''
59}};
60
61def format ArmBlBlxImm() {{
62 decode_block = '''
63 if (machInst.condCode == 0xF) {
64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
65 (bits(machInst, 24) << 1);
66 return new BlxImm(machInst, imm);
67 } else {
68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69 (ConditionCode)(uint32_t)machInst.condCode);
70 }
71 '''
72}};
73
74def format ArmBxClz() {{
75 decode_block = '''
76 {
77 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
78 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
79 if (OPCODE == 0x9) {
80 return new BxReg(machInst, rm,
81 (ConditionCode)(uint32_t)machInst.condCode);
82 } else if (OPCODE == 0xb) {
83 return new Clz(machInst, rd, rm);
84 } else {
85 return new Unknown(machInst);
86 }
87 }
88 '''
89}};
90
91def format ArmBlxReg() {{
92 decode_block = '''
93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
94 (ConditionCode)(uint32_t)machInst.condCode);
95 '''
96}};
97
98def format Thumb16CondBranchAndSvc() {{
99 decode_block = '''
100 if (bits(machInst, 11, 9) != 0x7) {
101 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1),
102 (ConditionCode)(uint32_t)bits(machInst, 11, 8));
103 } else if (bits(machInst, 8)) {
104 return new Svc(machInst);
105 } else {
106 // This space will not be allocated in the future.
|
129 } else {
130 return new WarnUnimplemented("smc", machInst);
131 }
132 } else if ((op & 0x38) != 0x38) {
133 const uint32_t s = bits(machInst, 26);
134 const uint32_t j1 = bits(machInst, 13);
135 const uint32_t j2 = bits(machInst, 11);
136 const uint32_t imm6 = bits(machInst, 21, 16);
137 const uint32_t imm11 = bits(machInst, 10, 0);
138 const int32_t imm = sext<21>((s << 20) |
139 (j2 << 19) | (j1 << 18) |
140 (imm6 << 12) | (imm11 << 1));
141 return new B(machInst, imm,
142 (ConditionCode)(uint32_t)bits(machInst, 25, 22));
143 } else {
144 switch (op) {
145 case 0x38:
146 {
147 const IntRegIndex rn =
148 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
149 const uint8_t byteMask = bits(machInst, 11, 8);
150 return new MsrCpsrReg(machInst, rn, byteMask);
151 }
152 case 0x39:
153 {
154 const IntRegIndex rn =
155 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
156 const uint8_t byteMask = bits(machInst, 11, 8);
157 return new MsrSpsrReg(machInst, rn, byteMask);
158 }
159 case 0x3a:
160 {
161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
164 return new WarnUnimplemented("cps", machInst);
165 } else if ((op2 & 0xf0) == 0xf0) {
166 return new WarnUnimplemented("dbg", machInst);
167 } else {
168 switch (op2) {
169 case 0x0:
170 return new NopInst(machInst);
171 case 0x1:
172 return new WarnUnimplemented("yield", machInst);
173 case 0x2:
174 return new WarnUnimplemented("wfe", machInst);
175 case 0x3:
176 return new WarnUnimplemented("wfi", machInst);
177 case 0x4:
178 return new WarnUnimplemented("sev", machInst);
179 default:
180 break;
181 }
182 }
183 break;
184 }
185 case 0x3b:
186 {
187 const uint32_t op = bits(machInst, 7, 4);
188 switch (op) {
189 case 0x0:
190 return new WarnUnimplemented("leavex", machInst);
191 case 0x1:
192 return new WarnUnimplemented("enterx", machInst);
193 case 0x2:
194 return new WarnUnimplemented("clrex", machInst);
195 case 0x4:
196 return new WarnUnimplemented("dsb", machInst);
197 case 0x5:
198 return new WarnUnimplemented("dmb", machInst);
199 case 0x6:
200 return new WarnUnimplemented("isb", machInst);
201 default:
202 break;
203 }
204 break;
205 }
206 case 0x3c:
207 return new WarnUnimplemented("bxj", machInst);
208 case 0x3d:
209 {
210 const uint32_t imm32 = bits(machInst, 7, 0);
211 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
212 imm32, false);
213 }
214 case 0x3e:
215 {
216 const IntRegIndex rd =
217 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
218 return new MrsCpsr(machInst, rd);
219 }
220 case 0x3f:
221 {
222 const IntRegIndex rd =
223 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
224 return new MrsSpsr(machInst, rd);
225 }
226 }
227 break;
228 }
229 case 0x1:
230 {
231 const uint32_t s = bits(machInst, 26);
232 const uint32_t i1 = !(bits(machInst, 13) ^ s);
233 const uint32_t i2 = !(bits(machInst, 11) ^ s);
234 const uint32_t imm10 = bits(machInst, 25, 16);
235 const uint32_t imm11 = bits(machInst, 10, 0);
236 const int32_t imm = sext<25>((s << 24) |
237 (i1 << 23) | (i2 << 22) |
238 (imm10 << 12) | (imm11 << 1));
239 return new B(machInst, imm, COND_UC);
240 }
241 case 0x4:
242 {
243 const uint32_t s = bits(machInst, 26);
244 const uint32_t i1 = !(bits(machInst, 13) ^ s);
245 const uint32_t i2 = !(bits(machInst, 11) ^ s);
246 const uint32_t imm10h = bits(machInst, 25, 16);
247 const uint32_t imm10l = bits(machInst, 10, 1);
248 const int32_t imm = sext<25>((s << 24) |
249 (i1 << 23) | (i2 << 22) |
250 (imm10h << 12) | (imm10l << 2));
251 return new BlxImm(machInst, imm);
252 }
253 case 0x5:
254 {
255 const uint32_t s = bits(machInst, 26);
256 const uint32_t i1 = !(bits(machInst, 13) ^ s);
257 const uint32_t i2 = !(bits(machInst, 11) ^ s);
258 const uint32_t imm10 = bits(machInst, 25, 16);
259 const uint32_t imm11 = bits(machInst, 10, 0);
260 const int32_t imm = sext<25>((s << 24) |
261 (i1 << 23) | (i2 << 22) |
262 (imm10 << 12) | (imm11 << 1));
263 return new Bl(machInst, imm, COND_UC);
264 }
265 default:
266 break;
267 }
268 return new Unknown(machInst);
269 }
270 '''
271}};
| 129 } else {
130 return new WarnUnimplemented("smc", machInst);
131 }
132 } else if ((op & 0x38) != 0x38) {
133 const uint32_t s = bits(machInst, 26);
134 const uint32_t j1 = bits(machInst, 13);
135 const uint32_t j2 = bits(machInst, 11);
136 const uint32_t imm6 = bits(machInst, 21, 16);
137 const uint32_t imm11 = bits(machInst, 10, 0);
138 const int32_t imm = sext<21>((s << 20) |
139 (j2 << 19) | (j1 << 18) |
140 (imm6 << 12) | (imm11 << 1));
141 return new B(machInst, imm,
142 (ConditionCode)(uint32_t)bits(machInst, 25, 22));
143 } else {
144 switch (op) {
145 case 0x38:
146 {
147 const IntRegIndex rn =
148 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
149 const uint8_t byteMask = bits(machInst, 11, 8);
150 return new MsrCpsrReg(machInst, rn, byteMask);
151 }
152 case 0x39:
153 {
154 const IntRegIndex rn =
155 (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
156 const uint8_t byteMask = bits(machInst, 11, 8);
157 return new MsrSpsrReg(machInst, rn, byteMask);
158 }
159 case 0x3a:
160 {
161 const uint32_t op1 = bits(machInst, 10, 8);
162 const uint32_t op2 = bits(machInst, 7, 0);
163 if (op1 != 0) {
164 return new WarnUnimplemented("cps", machInst);
165 } else if ((op2 & 0xf0) == 0xf0) {
166 return new WarnUnimplemented("dbg", machInst);
167 } else {
168 switch (op2) {
169 case 0x0:
170 return new NopInst(machInst);
171 case 0x1:
172 return new WarnUnimplemented("yield", machInst);
173 case 0x2:
174 return new WarnUnimplemented("wfe", machInst);
175 case 0x3:
176 return new WarnUnimplemented("wfi", machInst);
177 case 0x4:
178 return new WarnUnimplemented("sev", machInst);
179 default:
180 break;
181 }
182 }
183 break;
184 }
185 case 0x3b:
186 {
187 const uint32_t op = bits(machInst, 7, 4);
188 switch (op) {
189 case 0x0:
190 return new WarnUnimplemented("leavex", machInst);
191 case 0x1:
192 return new WarnUnimplemented("enterx", machInst);
193 case 0x2:
194 return new WarnUnimplemented("clrex", machInst);
195 case 0x4:
196 return new WarnUnimplemented("dsb", machInst);
197 case 0x5:
198 return new WarnUnimplemented("dmb", machInst);
199 case 0x6:
200 return new WarnUnimplemented("isb", machInst);
201 default:
202 break;
203 }
204 break;
205 }
206 case 0x3c:
207 return new WarnUnimplemented("bxj", machInst);
208 case 0x3d:
209 {
210 const uint32_t imm32 = bits(machInst, 7, 0);
211 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
212 imm32, false);
213 }
214 case 0x3e:
215 {
216 const IntRegIndex rd =
217 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
218 return new MrsCpsr(machInst, rd);
219 }
220 case 0x3f:
221 {
222 const IntRegIndex rd =
223 (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
224 return new MrsSpsr(machInst, rd);
225 }
226 }
227 break;
228 }
229 case 0x1:
230 {
231 const uint32_t s = bits(machInst, 26);
232 const uint32_t i1 = !(bits(machInst, 13) ^ s);
233 const uint32_t i2 = !(bits(machInst, 11) ^ s);
234 const uint32_t imm10 = bits(machInst, 25, 16);
235 const uint32_t imm11 = bits(machInst, 10, 0);
236 const int32_t imm = sext<25>((s << 24) |
237 (i1 << 23) | (i2 << 22) |
238 (imm10 << 12) | (imm11 << 1));
239 return new B(machInst, imm, COND_UC);
240 }
241 case 0x4:
242 {
243 const uint32_t s = bits(machInst, 26);
244 const uint32_t i1 = !(bits(machInst, 13) ^ s);
245 const uint32_t i2 = !(bits(machInst, 11) ^ s);
246 const uint32_t imm10h = bits(machInst, 25, 16);
247 const uint32_t imm10l = bits(machInst, 10, 1);
248 const int32_t imm = sext<25>((s << 24) |
249 (i1 << 23) | (i2 << 22) |
250 (imm10h << 12) | (imm10l << 2));
251 return new BlxImm(machInst, imm);
252 }
253 case 0x5:
254 {
255 const uint32_t s = bits(machInst, 26);
256 const uint32_t i1 = !(bits(machInst, 13) ^ s);
257 const uint32_t i2 = !(bits(machInst, 11) ^ s);
258 const uint32_t imm10 = bits(machInst, 25, 16);
259 const uint32_t imm11 = bits(machInst, 10, 0);
260 const int32_t imm = sext<25>((s << 24) |
261 (i1 << 23) | (i2 << 22) |
262 (imm10 << 12) | (imm11 << 1));
263 return new Bl(machInst, imm, COND_UC);
264 }
265 default:
266 break;
267 }
268 return new Unknown(machInst);
269 }
270 '''
271}};
|