1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Control transfer instructions 46// 47 48def format ArmBBlxImm() {{ 49 decode_block = ''' 50 if (machInst.condCode == 0xF) { 51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 52 (bits(machInst, 24) << 1); 53 return new BlxImm(machInst, imm); 54 } else { 55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2), 56 (ConditionCode)(uint32_t)machInst.condCode); 57 } 58 ''' 59}}; 60 61def format ArmBlBlxImm() {{ 62 decode_block = ''' 63 if (machInst.condCode == 0xF) { 64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 65 (bits(machInst, 24) << 1); 66 return new BlxImm(machInst, imm); 67 } else { 68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2), 69 (ConditionCode)(uint32_t)machInst.condCode); 70 } 71 ''' 72}}; 73
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Control transfer instructions 46// 47 48def format ArmBBlxImm() {{ 49 decode_block = ''' 50 if (machInst.condCode == 0xF) { 51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 52 (bits(machInst, 24) << 1); 53 return new BlxImm(machInst, imm); 54 } else { 55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2), 56 (ConditionCode)(uint32_t)machInst.condCode); 57 } 58 ''' 59}}; 60 61def format ArmBlBlxImm() {{ 62 decode_block = ''' 63 if (machInst.condCode == 0xF) { 64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 65 (bits(machInst, 24) << 1); 66 return new BlxImm(machInst, imm); 67 } else { 68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2), 69 (ConditionCode)(uint32_t)machInst.condCode); 70 } 71 ''' 72}}; 73
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78 ''' 79}}; 80 81def format ArmBlxReg() {{ 82 decode_block = ''' 83 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), 84 (ConditionCode)(uint32_t)machInst.condCode); 85 ''' 86}}; 87 88def format Thumb16CondBranchAndSvc() {{ 89 decode_block = ''' 90 if (bits(machInst, 11, 9) != 0x7) { 91 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1), 92 (ConditionCode)(uint32_t)bits(machInst, 11, 8)); 93 } else if (bits(machInst, 8)) { 94 return new Svc(machInst); 95 } else { 96 // This space will not be allocated in the future. 97 return new WarnUnimplemented("unimplemented", machInst); 98 } 99 ''' 100}}; 101 102def format Thumb16UncondBranch() {{ 103 decode_block = ''' 104 return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC); 105 ''' 106}}; 107 108def format Thumb32BranchesAndMiscCtrl() {{ 109 decode_block = ''' 110 { 111 const uint32_t op = bits(machInst, 26, 20); 112 const uint32_t op1 = bits(machInst, 14, 12); 113 switch (op1 & 0x5) { 114 case 0x0: 115 if (op == 127) { 116 if (op1 & 0x2) { 117 // Permanentl undefined. 118 return new WarnUnimplemented("undefined", machInst); 119 } else { 120 return new WarnUnimplemented("smc", machInst); 121 } 122 } else if ((op & 0x38) != 0x38) { 123 const uint32_t s = bits(machInst, 26); 124 const uint32_t j1 = bits(machInst, 13); 125 const uint32_t j2 = bits(machInst, 11); 126 const uint32_t imm6 = bits(machInst, 21, 16); 127 const uint32_t imm11 = bits(machInst, 10, 0); 128 const int32_t imm = sext<21>((s << 20) | 129 (j2 << 19) | (j1 << 18) | 130 (imm6 << 12) | (imm11 << 1)); 131 return new B(machInst, imm, 132 (ConditionCode)(uint32_t)bits(machInst, 25, 22)); 133 } else { 134 switch (op) { 135 case 0x38: 136 { 137 const IntRegIndex rn = 138 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 139 const uint8_t byteMask = bits(machInst, 11, 8); 140 return new MsrCpsrReg(machInst, rn, byteMask); 141 } 142 case 0x39: 143 { 144 const IntRegIndex rn = 145 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 146 const uint8_t byteMask = bits(machInst, 11, 8); 147 return new MsrSpsrReg(machInst, rn, byteMask); 148 } 149 case 0x3a: 150 { 151 const uint32_t op1 = bits(machInst, 10, 8); 152 const uint32_t op2 = bits(machInst, 7, 0); 153 if (op1 != 0) { 154 return new WarnUnimplemented("cps", machInst); 155 } else if ((op2 & 0xf0) == 0xf0) { 156 return new WarnUnimplemented("dbg", machInst); 157 } else { 158 switch (op2) { 159 case 0x0: 160 return new NopInst(machInst); 161 case 0x1: 162 return new WarnUnimplemented("yield", machInst); 163 case 0x2: 164 return new WarnUnimplemented("wfe", machInst); 165 case 0x3: 166 return new WarnUnimplemented("wfi", machInst); 167 case 0x4: 168 return new WarnUnimplemented("sev", machInst); 169 default: 170 break; 171 } 172 } 173 break; 174 } 175 case 0x3b: 176 { 177 const uint32_t op = bits(machInst, 7, 4); 178 switch (op) { 179 case 0x0: 180 return new WarnUnimplemented("leavex", machInst); 181 case 0x1: 182 return new WarnUnimplemented("enterx", machInst); 183 case 0x2: 184 return new WarnUnimplemented("clrex", machInst); 185 case 0x4: 186 return new WarnUnimplemented("dsb", machInst); 187 case 0x5: 188 return new WarnUnimplemented("dmb", machInst); 189 case 0x6: 190 return new WarnUnimplemented("isb", machInst); 191 default: 192 break; 193 } 194 break; 195 } 196 case 0x3c: 197 return new WarnUnimplemented("bxj", machInst); 198 case 0x3d: 199 { 200 const uint32_t imm32 = bits(machInst, 7, 0); 201 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR, 202 imm32, false); 203 } 204 case 0x3e: 205 { 206 const IntRegIndex rd = 207 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 208 return new MrsCpsr(machInst, rd); 209 } 210 case 0x3f: 211 { 212 const IntRegIndex rd = 213 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 214 return new MrsSpsr(machInst, rd); 215 } 216 } 217 break; 218 } 219 case 0x1: 220 { 221 const uint32_t s = bits(machInst, 26); 222 const uint32_t i1 = !(bits(machInst, 13) ^ s); 223 const uint32_t i2 = !(bits(machInst, 11) ^ s); 224 const uint32_t imm10 = bits(machInst, 25, 16); 225 const uint32_t imm11 = bits(machInst, 10, 0); 226 const int32_t imm = sext<25>((s << 24) | 227 (i1 << 23) | (i2 << 22) | 228 (imm10 << 12) | (imm11 << 1)); 229 return new B(machInst, imm, COND_UC); 230 } 231 case 0x4: 232 { 233 const uint32_t s = bits(machInst, 26); 234 const uint32_t i1 = !(bits(machInst, 13) ^ s); 235 const uint32_t i2 = !(bits(machInst, 11) ^ s); 236 const uint32_t imm10h = bits(machInst, 25, 16); 237 const uint32_t imm10l = bits(machInst, 10, 1); 238 const int32_t imm = sext<25>((s << 24) | 239 (i1 << 23) | (i2 << 22) | 240 (imm10h << 12) | (imm10l << 2)); 241 return new BlxImm(machInst, imm); 242 } 243 case 0x5: 244 { 245 const uint32_t s = bits(machInst, 26); 246 const uint32_t i1 = !(bits(machInst, 13) ^ s); 247 const uint32_t i2 = !(bits(machInst, 11) ^ s); 248 const uint32_t imm10 = bits(machInst, 25, 16); 249 const uint32_t imm11 = bits(machInst, 10, 0); 250 const int32_t imm = sext<25>((s << 24) | 251 (i1 << 23) | (i2 << 22) | 252 (imm10 << 12) | (imm11 << 1)); 253 return new Bl(machInst, imm, COND_UC); 254 } 255 default: 256 break; 257 } 258 return new Unknown(machInst); 259 } 260 ''' 261}};
| 88 ''' 89}}; 90 91def format ArmBlxReg() {{ 92 decode_block = ''' 93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), 94 (ConditionCode)(uint32_t)machInst.condCode); 95 ''' 96}}; 97 98def format Thumb16CondBranchAndSvc() {{ 99 decode_block = ''' 100 if (bits(machInst, 11, 9) != 0x7) { 101 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1), 102 (ConditionCode)(uint32_t)bits(machInst, 11, 8)); 103 } else if (bits(machInst, 8)) { 104 return new Svc(machInst); 105 } else { 106 // This space will not be allocated in the future. 107 return new WarnUnimplemented("unimplemented", machInst); 108 } 109 ''' 110}}; 111 112def format Thumb16UncondBranch() {{ 113 decode_block = ''' 114 return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC); 115 ''' 116}}; 117 118def format Thumb32BranchesAndMiscCtrl() {{ 119 decode_block = ''' 120 { 121 const uint32_t op = bits(machInst, 26, 20); 122 const uint32_t op1 = bits(machInst, 14, 12); 123 switch (op1 & 0x5) { 124 case 0x0: 125 if (op == 127) { 126 if (op1 & 0x2) { 127 // Permanentl undefined. 128 return new WarnUnimplemented("undefined", machInst); 129 } else { 130 return new WarnUnimplemented("smc", machInst); 131 } 132 } else if ((op & 0x38) != 0x38) { 133 const uint32_t s = bits(machInst, 26); 134 const uint32_t j1 = bits(machInst, 13); 135 const uint32_t j2 = bits(machInst, 11); 136 const uint32_t imm6 = bits(machInst, 21, 16); 137 const uint32_t imm11 = bits(machInst, 10, 0); 138 const int32_t imm = sext<21>((s << 20) | 139 (j2 << 19) | (j1 << 18) | 140 (imm6 << 12) | (imm11 << 1)); 141 return new B(machInst, imm, 142 (ConditionCode)(uint32_t)bits(machInst, 25, 22)); 143 } else { 144 switch (op) { 145 case 0x38: 146 { 147 const IntRegIndex rn = 148 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 149 const uint8_t byteMask = bits(machInst, 11, 8); 150 return new MsrCpsrReg(machInst, rn, byteMask); 151 } 152 case 0x39: 153 { 154 const IntRegIndex rn = 155 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 156 const uint8_t byteMask = bits(machInst, 11, 8); 157 return new MsrSpsrReg(machInst, rn, byteMask); 158 } 159 case 0x3a: 160 { 161 const uint32_t op1 = bits(machInst, 10, 8); 162 const uint32_t op2 = bits(machInst, 7, 0); 163 if (op1 != 0) { 164 return new WarnUnimplemented("cps", machInst); 165 } else if ((op2 & 0xf0) == 0xf0) { 166 return new WarnUnimplemented("dbg", machInst); 167 } else { 168 switch (op2) { 169 case 0x0: 170 return new NopInst(machInst); 171 case 0x1: 172 return new WarnUnimplemented("yield", machInst); 173 case 0x2: 174 return new WarnUnimplemented("wfe", machInst); 175 case 0x3: 176 return new WarnUnimplemented("wfi", machInst); 177 case 0x4: 178 return new WarnUnimplemented("sev", machInst); 179 default: 180 break; 181 } 182 } 183 break; 184 } 185 case 0x3b: 186 { 187 const uint32_t op = bits(machInst, 7, 4); 188 switch (op) { 189 case 0x0: 190 return new WarnUnimplemented("leavex", machInst); 191 case 0x1: 192 return new WarnUnimplemented("enterx", machInst); 193 case 0x2: 194 return new WarnUnimplemented("clrex", machInst); 195 case 0x4: 196 return new WarnUnimplemented("dsb", machInst); 197 case 0x5: 198 return new WarnUnimplemented("dmb", machInst); 199 case 0x6: 200 return new WarnUnimplemented("isb", machInst); 201 default: 202 break; 203 } 204 break; 205 } 206 case 0x3c: 207 return new WarnUnimplemented("bxj", machInst); 208 case 0x3d: 209 { 210 const uint32_t imm32 = bits(machInst, 7, 0); 211 return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR, 212 imm32, false); 213 } 214 case 0x3e: 215 { 216 const IntRegIndex rd = 217 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 218 return new MrsCpsr(machInst, rd); 219 } 220 case 0x3f: 221 { 222 const IntRegIndex rd = 223 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 224 return new MrsSpsr(machInst, rd); 225 } 226 } 227 break; 228 } 229 case 0x1: 230 { 231 const uint32_t s = bits(machInst, 26); 232 const uint32_t i1 = !(bits(machInst, 13) ^ s); 233 const uint32_t i2 = !(bits(machInst, 11) ^ s); 234 const uint32_t imm10 = bits(machInst, 25, 16); 235 const uint32_t imm11 = bits(machInst, 10, 0); 236 const int32_t imm = sext<25>((s << 24) | 237 (i1 << 23) | (i2 << 22) | 238 (imm10 << 12) | (imm11 << 1)); 239 return new B(machInst, imm, COND_UC); 240 } 241 case 0x4: 242 { 243 const uint32_t s = bits(machInst, 26); 244 const uint32_t i1 = !(bits(machInst, 13) ^ s); 245 const uint32_t i2 = !(bits(machInst, 11) ^ s); 246 const uint32_t imm10h = bits(machInst, 25, 16); 247 const uint32_t imm10l = bits(machInst, 10, 1); 248 const int32_t imm = sext<25>((s << 24) | 249 (i1 << 23) | (i2 << 22) | 250 (imm10h << 12) | (imm10l << 2)); 251 return new BlxImm(machInst, imm); 252 } 253 case 0x5: 254 { 255 const uint32_t s = bits(machInst, 26); 256 const uint32_t i1 = !(bits(machInst, 13) ^ s); 257 const uint32_t i2 = !(bits(machInst, 11) ^ s); 258 const uint32_t imm10 = bits(machInst, 25, 16); 259 const uint32_t imm11 = bits(machInst, 10, 0); 260 const int32_t imm = sext<25>((s << 24) | 261 (i1 << 23) | (i2 << 22) | 262 (imm10 << 12) | (imm11 << 1)); 263 return new Bl(machInst, imm, COND_UC); 264 } 265 default: 266 break; 267 } 268 return new Unknown(machInst); 269 } 270 ''' 271}};
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