4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Control transfer instructions 46// 47 48def format ArmBBlxImm() {{ 49 decode_block = ''' 50 if (machInst.condCode == 0xF) { 51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 52 (bits(machInst, 24) << 1); 53 return new BlxImm(machInst, imm, COND_UC); 54 } else { 55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2), 56 (ConditionCode)(uint32_t)machInst.condCode); 57 } 58 ''' 59}}; 60 61def format ArmBlBlxImm() {{ 62 decode_block = ''' 63 if (machInst.condCode == 0xF) { 64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 65 (bits(machInst, 24) << 1); 66 return new BlxImm(machInst, imm, COND_UC); 67 } else { 68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2), 69 (ConditionCode)(uint32_t)machInst.condCode); 70 } 71 ''' 72}}; 73 74def format ArmBxClz() {{ 75 decode_block = ''' 76 { 77 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 78 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 79 if (OPCODE == 0x9) { 80 return new BxReg(machInst, rm, 81 (ConditionCode)(uint32_t)machInst.condCode); 82 } else if (OPCODE == 0xb) { 83 return new Clz(machInst, rd, rm); 84 } else { 85 return new Unknown(machInst); 86 } 87 } 88 ''' 89}}; 90 91def format ArmBlxReg() {{ 92 decode_block = ''' 93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), 94 (ConditionCode)(uint32_t)machInst.condCode); 95 ''' 96}}; 97 98def format Thumb16CondBranchAndSvc() {{ 99 decode_block = ''' 100 if (bits(machInst, 11, 9) != 0x7) { 101 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1), 102 (ConditionCode)(uint32_t)bits(machInst, 11, 8)); 103 } else if (bits(machInst, 8)) { 104 return new Svc(machInst, bits(machInst, 7, 0)); 105 } else { 106 // This space will not be allocated in the future. 107 return new Unknown(machInst); 108 } 109 ''' 110}}; 111 112def format Thumb16UncondBranch() {{ 113 decode_block = ''' 114 return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC); 115 ''' 116}}; 117 118def format Thumb32BranchesAndMiscCtrl() {{ 119 decode_block = ''' 120 { 121 const uint32_t op = bits(machInst, 26, 20); 122 const uint32_t op1 = bits(machInst, 14, 12); 123 switch (op1 & 0x5) { 124 case 0x0: 125 if (op == 127) { 126 if (op1 & 0x2) { 127 // Permanently undefined. 128 return new Unknown(machInst); 129 } else { 130 return new Smc(machInst); 131 } 132 } else if ((op & 0x38) != 0x38) { 133 const uint32_t s = bits(machInst, 26); 134 const uint32_t j1 = bits(machInst, 13); 135 const uint32_t j2 = bits(machInst, 11); 136 const uint32_t imm6 = bits(machInst, 21, 16); 137 const uint32_t imm11 = bits(machInst, 10, 0); 138 const int32_t imm = sext<21>((s << 20) | 139 (j2 << 19) | (j1 << 18) | 140 (imm6 << 12) | (imm11 << 1)); 141 return new B(machInst, imm, 142 (ConditionCode)(uint32_t)bits(machInst, 25, 22)); 143 } else { 144 // HIGH: 12-11=10, LOW: 15-14=00, 12=0 145 switch (op) { 146 case 0x38: 147 case 0x39: 148 { 149 const IntRegIndex rn = 150 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 151 const uint8_t byteMask = bits(machInst, 11, 8); 152 const bool r = bits(machInst, 20); 153 if (bits(machInst, 5)) { 154 const uint8_t sysM = (bits(machInst, 4) << 4) | 155 byteMask; 156 return new MsrBankedReg(machInst, rn, sysM, r); 157 } else { 158 if (r) { 159 return new MsrSpsrReg(machInst, rn, byteMask); 160 } else { 161 return new MsrCpsrReg(machInst, rn, byteMask); 162 } 163 } 164 } 165 case 0x3a: 166 { 167 const uint32_t op1 = bits(machInst, 10, 8); 168 const uint32_t op2 = bits(machInst, 7, 0); 169 if (op1 != 0) { 170 const bool enable = bits(machInst, 10, 9) == 0x2; 171 const uint32_t mods = bits(machInst, 8, 0) | 172 ((enable ? 1 : 0) << 9); 173 return new Cps(machInst, mods); 174 } else if ((op2 & 0xf0) == 0xf0) { 175 return new Dbg(machInst); 176 } else { 177 switch (op2) { 178 case 0x0: 179 return new NopInst(machInst); 180 case 0x1: 181 return new YieldInst(machInst); 182 case 0x2: 183 return new WfeInst(machInst); 184 case 0x3: 185 return new WfiInst(machInst); 186 case 0x4: 187 return new SevInst(machInst); 188 default: 189 break; 190 } 191 } 192 break; 193 } 194 case 0x3b: 195 { 196 const uint32_t op = bits(machInst, 7, 4); 197 switch (op) { 198 case 0x0: 199 return new Leavex(machInst); 200 case 0x1: 201 return new Enterx(machInst); 202 case 0x2: 203 return new Clrex(machInst); 204 case 0x4: 205 return new Dsb(machInst, 0); 206 case 0x5: 207 return new Dmb(machInst, 0); 208 case 0x6: 209 return new Isb(machInst, 0); 210 default: 211 break; 212 } 213 break; 214 } 215 case 0x3c: 216 { 217 return new BxjReg(machInst, 218 (IntRegIndex)(uint32_t)bits(machInst, 19, 16), 219 COND_UC); 220 } 221 case 0x3d: 222 { 223 const uint32_t imm32 = bits(machInst, 7, 0); 224 if (imm32 == 0) { 225 return new Eret(machInst); 226 } else { 227 return new SubsImmPclr(machInst, INTREG_PC, 228 INTREG_LR, imm32, false); 229 } 230 } 231 case 0x3e: 232 case 0x3f: 233 { 234 235 const IntRegIndex rd = 236 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 237 const bool r = bits(machInst, 20); 238 if (bits(machInst, 5)) { 239 const uint8_t sysM = (bits(machInst, 4) << 4) | 240 bits(machInst, 11, 8); 241 return new MrsBankedReg(machInst, rd, sysM, r); 242 } else { 243 if (r) { 244 return new MrsSpsr(machInst, rd); 245 } else { 246 return new MrsCpsr(machInst, rd); 247 } 248 } 249 }
| 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Control transfer instructions 46// 47 48def format ArmBBlxImm() {{ 49 decode_block = ''' 50 if (machInst.condCode == 0xF) { 51 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 52 (bits(machInst, 24) << 1); 53 return new BlxImm(machInst, imm, COND_UC); 54 } else { 55 return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2), 56 (ConditionCode)(uint32_t)machInst.condCode); 57 } 58 ''' 59}}; 60 61def format ArmBlBlxImm() {{ 62 decode_block = ''' 63 if (machInst.condCode == 0xF) { 64 int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 65 (bits(machInst, 24) << 1); 66 return new BlxImm(machInst, imm, COND_UC); 67 } else { 68 return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2), 69 (ConditionCode)(uint32_t)machInst.condCode); 70 } 71 ''' 72}}; 73 74def format ArmBxClz() {{ 75 decode_block = ''' 76 { 77 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 78 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 79 if (OPCODE == 0x9) { 80 return new BxReg(machInst, rm, 81 (ConditionCode)(uint32_t)machInst.condCode); 82 } else if (OPCODE == 0xb) { 83 return new Clz(machInst, rd, rm); 84 } else { 85 return new Unknown(machInst); 86 } 87 } 88 ''' 89}}; 90 91def format ArmBlxReg() {{ 92 decode_block = ''' 93 return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), 94 (ConditionCode)(uint32_t)machInst.condCode); 95 ''' 96}}; 97 98def format Thumb16CondBranchAndSvc() {{ 99 decode_block = ''' 100 if (bits(machInst, 11, 9) != 0x7) { 101 return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1), 102 (ConditionCode)(uint32_t)bits(machInst, 11, 8)); 103 } else if (bits(machInst, 8)) { 104 return new Svc(machInst, bits(machInst, 7, 0)); 105 } else { 106 // This space will not be allocated in the future. 107 return new Unknown(machInst); 108 } 109 ''' 110}}; 111 112def format Thumb16UncondBranch() {{ 113 decode_block = ''' 114 return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC); 115 ''' 116}}; 117 118def format Thumb32BranchesAndMiscCtrl() {{ 119 decode_block = ''' 120 { 121 const uint32_t op = bits(machInst, 26, 20); 122 const uint32_t op1 = bits(machInst, 14, 12); 123 switch (op1 & 0x5) { 124 case 0x0: 125 if (op == 127) { 126 if (op1 & 0x2) { 127 // Permanently undefined. 128 return new Unknown(machInst); 129 } else { 130 return new Smc(machInst); 131 } 132 } else if ((op & 0x38) != 0x38) { 133 const uint32_t s = bits(machInst, 26); 134 const uint32_t j1 = bits(machInst, 13); 135 const uint32_t j2 = bits(machInst, 11); 136 const uint32_t imm6 = bits(machInst, 21, 16); 137 const uint32_t imm11 = bits(machInst, 10, 0); 138 const int32_t imm = sext<21>((s << 20) | 139 (j2 << 19) | (j1 << 18) | 140 (imm6 << 12) | (imm11 << 1)); 141 return new B(machInst, imm, 142 (ConditionCode)(uint32_t)bits(machInst, 25, 22)); 143 } else { 144 // HIGH: 12-11=10, LOW: 15-14=00, 12=0 145 switch (op) { 146 case 0x38: 147 case 0x39: 148 { 149 const IntRegIndex rn = 150 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 151 const uint8_t byteMask = bits(machInst, 11, 8); 152 const bool r = bits(machInst, 20); 153 if (bits(machInst, 5)) { 154 const uint8_t sysM = (bits(machInst, 4) << 4) | 155 byteMask; 156 return new MsrBankedReg(machInst, rn, sysM, r); 157 } else { 158 if (r) { 159 return new MsrSpsrReg(machInst, rn, byteMask); 160 } else { 161 return new MsrCpsrReg(machInst, rn, byteMask); 162 } 163 } 164 } 165 case 0x3a: 166 { 167 const uint32_t op1 = bits(machInst, 10, 8); 168 const uint32_t op2 = bits(machInst, 7, 0); 169 if (op1 != 0) { 170 const bool enable = bits(machInst, 10, 9) == 0x2; 171 const uint32_t mods = bits(machInst, 8, 0) | 172 ((enable ? 1 : 0) << 9); 173 return new Cps(machInst, mods); 174 } else if ((op2 & 0xf0) == 0xf0) { 175 return new Dbg(machInst); 176 } else { 177 switch (op2) { 178 case 0x0: 179 return new NopInst(machInst); 180 case 0x1: 181 return new YieldInst(machInst); 182 case 0x2: 183 return new WfeInst(machInst); 184 case 0x3: 185 return new WfiInst(machInst); 186 case 0x4: 187 return new SevInst(machInst); 188 default: 189 break; 190 } 191 } 192 break; 193 } 194 case 0x3b: 195 { 196 const uint32_t op = bits(machInst, 7, 4); 197 switch (op) { 198 case 0x0: 199 return new Leavex(machInst); 200 case 0x1: 201 return new Enterx(machInst); 202 case 0x2: 203 return new Clrex(machInst); 204 case 0x4: 205 return new Dsb(machInst, 0); 206 case 0x5: 207 return new Dmb(machInst, 0); 208 case 0x6: 209 return new Isb(machInst, 0); 210 default: 211 break; 212 } 213 break; 214 } 215 case 0x3c: 216 { 217 return new BxjReg(machInst, 218 (IntRegIndex)(uint32_t)bits(machInst, 19, 16), 219 COND_UC); 220 } 221 case 0x3d: 222 { 223 const uint32_t imm32 = bits(machInst, 7, 0); 224 if (imm32 == 0) { 225 return new Eret(machInst); 226 } else { 227 return new SubsImmPclr(machInst, INTREG_PC, 228 INTREG_LR, imm32, false); 229 } 230 } 231 case 0x3e: 232 case 0x3f: 233 { 234 235 const IntRegIndex rd = 236 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 237 const bool r = bits(machInst, 20); 238 if (bits(machInst, 5)) { 239 const uint8_t sysM = (bits(machInst, 4) << 4) | 240 bits(machInst, 11, 8); 241 return new MrsBankedReg(machInst, rd, sysM, r); 242 } else { 243 if (r) { 244 return new MrsSpsr(machInst, rd); 245 } else { 246 return new MrsCpsr(machInst, rd); 247 } 248 } 249 }
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251 { 252 uint32_t imm16 = (bits(machInst, 19, 16) << 12) | 253 (bits(machInst, 11, 0) << 0); 254 return new Hvc(machInst, imm16); 255 } 256 } 257 break; 258 } 259 case 0x1: 260 { 261 const uint32_t s = bits(machInst, 26); 262 const uint32_t i1 = !(bits(machInst, 13) ^ s); 263 const uint32_t i2 = !(bits(machInst, 11) ^ s); 264 const uint32_t imm10 = bits(machInst, 25, 16); 265 const uint32_t imm11 = bits(machInst, 10, 0); 266 const int32_t imm = sext<25>((s << 24) | 267 (i1 << 23) | (i2 << 22) | 268 (imm10 << 12) | (imm11 << 1)); 269 return new B(machInst, imm, COND_UC); 270 } 271 case 0x4: 272 { 273 if (bits(machInst, 0) == 1) { 274 return new Unknown(machInst); 275 } 276 const uint32_t s = bits(machInst, 26); 277 const uint32_t i1 = !(bits(machInst, 13) ^ s); 278 const uint32_t i2 = !(bits(machInst, 11) ^ s); 279 const uint32_t imm10h = bits(machInst, 25, 16); 280 const uint32_t imm10l = bits(machInst, 10, 1); 281 const int32_t imm = sext<25>((s << 24) | 282 (i1 << 23) | (i2 << 22) | 283 (imm10h << 12) | (imm10l << 2)); 284 return new BlxImm(machInst, imm, COND_UC); 285 } 286 case 0x5: 287 { 288 const uint32_t s = bits(machInst, 26); 289 const uint32_t i1 = !(bits(machInst, 13) ^ s); 290 const uint32_t i2 = !(bits(machInst, 11) ^ s); 291 const uint32_t imm10 = bits(machInst, 25, 16); 292 const uint32_t imm11 = bits(machInst, 10, 0); 293 const int32_t imm = sext<25>((s << 24) | 294 (i1 << 23) | (i2 << 22) | 295 (imm10 << 12) | (imm11 << 1)); 296 return new Bl(machInst, imm, COND_UC); 297 } 298 default: 299 break; 300 } 301 return new Unknown(machInst); 302 } 303 ''' 304}};
| 251 { 252 uint32_t imm16 = (bits(machInst, 19, 16) << 12) | 253 (bits(machInst, 11, 0) << 0); 254 return new Hvc(machInst, imm16); 255 } 256 } 257 break; 258 } 259 case 0x1: 260 { 261 const uint32_t s = bits(machInst, 26); 262 const uint32_t i1 = !(bits(machInst, 13) ^ s); 263 const uint32_t i2 = !(bits(machInst, 11) ^ s); 264 const uint32_t imm10 = bits(machInst, 25, 16); 265 const uint32_t imm11 = bits(machInst, 10, 0); 266 const int32_t imm = sext<25>((s << 24) | 267 (i1 << 23) | (i2 << 22) | 268 (imm10 << 12) | (imm11 << 1)); 269 return new B(machInst, imm, COND_UC); 270 } 271 case 0x4: 272 { 273 if (bits(machInst, 0) == 1) { 274 return new Unknown(machInst); 275 } 276 const uint32_t s = bits(machInst, 26); 277 const uint32_t i1 = !(bits(machInst, 13) ^ s); 278 const uint32_t i2 = !(bits(machInst, 11) ^ s); 279 const uint32_t imm10h = bits(machInst, 25, 16); 280 const uint32_t imm10l = bits(machInst, 10, 1); 281 const int32_t imm = sext<25>((s << 24) | 282 (i1 << 23) | (i2 << 22) | 283 (imm10h << 12) | (imm10l << 2)); 284 return new BlxImm(machInst, imm, COND_UC); 285 } 286 case 0x5: 287 { 288 const uint32_t s = bits(machInst, 26); 289 const uint32_t i1 = !(bits(machInst, 13) ^ s); 290 const uint32_t i2 = !(bits(machInst, 11) ^ s); 291 const uint32_t imm10 = bits(machInst, 25, 16); 292 const uint32_t imm11 = bits(machInst, 10, 0); 293 const int32_t imm = sext<25>((s << 24) | 294 (i1 << 23) | (i2 << 22) | 295 (imm10 << 12) | (imm11 << 1)); 296 return new Bl(machInst, imm, COND_UC); 297 } 298 default: 299 break; 300 } 301 return new Unknown(machInst); 302 } 303 ''' 304}};
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