aarch64.isa (13354:c1bdac713ae5) aarch64.isa (13355:41e94570fafa)
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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364 case 0x4:
365 switch (op2 & 0x1) {
366 case 0x0:
367 return new WarnUnimplemented(
368 "bti", machInst);
369 }
370 break;
371 }
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 355 unchanged lines hidden (view full) ---

364 case 0x4:
365 switch (op2 & 0x1) {
366 case 0x0:
367 return new WarnUnimplemented(
368 "bti", machInst);
369 }
370 break;
371 }
372 return new Unknown64(machInst);
372 return new WarnUnimplemented(
373 "unallocated_hint", machInst);
373 } else if (crn == 0x3 && op1 == 0x3) {
374 switch (op2) {
375 case 0x2:
376 return new Clrex64(machInst);
377 case 0x4:
378 return new Dsb64(machInst);
379 case 0x5:
380 return new Dmb64(machInst);

--- 1928 unchanged lines hidden --- 		374 } else if (crn == 0x3 && op1 == 0x3) {
375 switch (op2) {
376 case 0x2:
377 return new Clrex64(machInst);
378 case 0x4:
379 return new Dsb64(machInst);
380 case 0x5:
381 return new Dmb64(machInst);

--- 1928 unchanged lines hidden ---