aarch64.isa (13171:8d3d2b1f1ca3) aarch64.isa (13354:c1bdac713ae5)
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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287 uint8_t crm = bits(machInst, 11, 8);
288 uint8_t op2 = bits(machInst, 7, 5);
289 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
290 switch (op0) {
291 case 0x0:
292 if (rt != 0x1f || l)
293 return new Unknown64(machInst);
294 if (crn == 0x2 && op1 == 0x3) {
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 278 unchanged lines hidden (view full) ---

287 uint8_t crm = bits(machInst, 11, 8);
288 uint8_t op2 = bits(machInst, 7, 5);
289 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
290 switch (op0) {
291 case 0x0:
292 if (rt != 0x1f || l)
293 return new Unknown64(machInst);
294 if (crn == 0x2 && op1 == 0x3) {
295 switch (op2) {
295 switch (crm) {
296 case 0x0:
296 case 0x0:
297 return new NopInst(machInst);
297 switch (op2) {
298 case 0x0:
299 return new NopInst(machInst);
300 case 0x1:
301 return new YieldInst(machInst);
302 case 0x2:
303 return new WfeInst(machInst);
304 case 0x3:
305 return new WfiInst(machInst);
306 case 0x4:
307 return new SevInst(machInst);
308 case 0x5:
309 return new SevlInst(machInst);
310 }
311 break;
298 case 0x1:
312 case 0x1:
299 return new YieldInst(machInst);
313 switch (op2) {
314 case 0x0:
315 return new WarnUnimplemented(
316 "pacia", machInst);
317 case 0x2:
318 return new WarnUnimplemented(
319 "pacib", machInst);
320 case 0x4:
321 return new WarnUnimplemented(
322 "autia", machInst);
323 case 0x6:
324 return new WarnUnimplemented(
325 "autib", machInst);
326 }
327 break;
300 case 0x2:
328 case 0x2:
301 return new WfeInst(machInst);
329 switch (op2) {
330 case 0x0:
331 return new WarnUnimplemented(
332 "esb", machInst);
333 case 0x1:
334 return new WarnUnimplemented(
335 "psb csync", machInst);
336 case 0x2:
337 return new WarnUnimplemented(
338 "tsb csync", machInst);
339 case 0x4:
340 return new WarnUnimplemented(
341 "csdb", machInst);
342 }
343 break;
302 case 0x3:
344 case 0x3:
303 return new WfiInst(machInst);
345 switch (op2) {
346 case 0x0:
347 case 0x1:
348 return new WarnUnimplemented(
349 "pacia", machInst);
350 case 0x2:
351 case 0x3:
352 return new WarnUnimplemented(
353 "pacib", machInst);
354 case 0x4:
355 case 0x5:
356 return new WarnUnimplemented(
357 "autia", machInst);
358 case 0x6:
359 case 0x7:
360 return new WarnUnimplemented(
361 "autib", machInst);
362 }
363 break;
304 case 0x4:
364 case 0x4:
305 return new SevInst(machInst);
306 case 0x5:
307 return new SevlInst(machInst);
308 default:
309 return new Unknown64(machInst);
365 switch (op2 & 0x1) {
366 case 0x0:
367 return new WarnUnimplemented(
368 "bti", machInst);
369 }
370 break;
310 }
371 }
372 return new Unknown64(machInst);
311 } else if (crn == 0x3 && op1 == 0x3) {
312 switch (op2) {
313 case 0x2:
314 return new Clrex64(machInst);
315 case 0x4:
316 return new Dsb64(machInst);
317 case 0x5:
318 return new Dmb64(machInst);

--- 1928 unchanged lines hidden --- 		373 } else if (crn == 0x3 && op1 == 0x3) {
374 switch (op2) {
375 case 0x2:
376 return new Clrex64(machInst);
377 case 0x4:
378 return new Dsb64(machInst);
379 case 0x5:
380 return new Dmb64(machInst);

--- 1928 unchanged lines hidden ---