aarch64.isa (12597:a2848203dcd0) aarch64.isa (12673:b862f22eeed9)
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 355 unchanged lines hidden (view full) ---

364 (miscReg == MISCREG_DC_CVAC_Xt) ||
365 (miscReg == MISCREG_DC_IVAC_Xt) ||
366 (miscReg == MISCREG_DC_ZVA_Xt)) {
367 return new Unknown64(machInst);
368 }
369 }
370 // Check for invalid registers
371 if (miscReg == MISCREG_UNKNOWN) {
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 355 unchanged lines hidden (view full) ---

364 (miscReg == MISCREG_DC_CVAC_Xt) ||
365 (miscReg == MISCREG_DC_IVAC_Xt) ||
366 (miscReg == MISCREG_DC_ZVA_Xt)) {
367 return new Unknown64(machInst);
368 }
369 }
370 // Check for invalid registers
371 if (miscReg == MISCREG_UNKNOWN) {
372 return new Unknown64(machInst);
372 auto full_mnemonic =
373 csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d",
374 read ? "mrs" : "msr",
375 op0, op1, crn, crm, op2);
376
377 return new FailUnimplemented(read ? "mrs" : "msr",
378 machInst, full_mnemonic);
379
373 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
374 if (miscReg == MISCREG_NZCV) {
375 if (read)
376 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg);
377 else
378 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt);
379 }
380 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt);

--- 1778 unchanged lines hidden --- 		380 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
381 if (miscReg == MISCREG_NZCV) {
382 if (read)
383 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg);
384 else
385 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt);
386 }
387 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt);

--- 1778 unchanged lines hidden ---