aarch64.isa (12258:08990d24fe41) | aarch64.isa (12280:a44a2326a02b) |
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1// Copyright (c) 2011-2016 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 355 unchanged lines hidden (view full) --- 364 else 365 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 366 } 367 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 368 if (miscReg == MISCREG_DC_ZVA_Xt && !read) 369 return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); 370 371 if (read) { | 1// Copyright (c) 2011-2016 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 355 unchanged lines hidden (view full) --- 364 else 365 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 366 } 367 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 368 if (miscReg == MISCREG_DC_ZVA_Xt && !read) 369 return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); 370 371 if (read) { |
372 StaticInstPtr si = new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); | 372 StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); |
373 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 374 si->setFlag(StaticInst::IsUnverifiable); 375 return si; | 373 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 374 si->setFlag(StaticInst::IsUnverifiable); 375 return si; |
376 } else 377 return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss); | 376 } else { 377 return new Msr64(machInst, miscReg, rt, iss); 378 } |
378 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 379 std::string full_mnem = csprintf("%s %s", 380 read ? "mrs" : "msr", miscRegName[miscReg]); 381 return new WarnUnimplemented(read ? "mrs" : "msr", 382 machInst, full_mnem); 383 } else { 384 return new FailUnimplemented(read ? "mrs" : "msr", 385 machInst, --- 1699 unchanged lines hidden --- | 379 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 380 std::string full_mnem = csprintf("%s %s", 381 read ? "mrs" : "msr", miscRegName[miscReg]); 382 return new WarnUnimplemented(read ? "mrs" : "msr", 383 machInst, full_mnem); 384 } else { 385 return new FailUnimplemented(read ? "mrs" : "msr", 386 machInst, --- 1699 unchanged lines hidden --- |