aarch64.isa (10506:aa23216161fa) aarch64.isa (11165:d90aec9435bd)
1// Copyright (c) 2011-2014 ARM Limited
1// Copyright (c) 2011-2015 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated

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41output header {{
42namespace Aarch64
43{
44 StaticInstPtr decodeDataProcImm(ExtMachInst machInst);
45 StaticInstPtr decodeBranchExcSys(ExtMachInst machInst);
46 StaticInstPtr decodeLoadsStores(ExtMachInst machInst);
47 StaticInstPtr decodeDataProcReg(ExtMachInst machInst);
48
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated

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41output header {{
42namespace Aarch64
43{
44 StaticInstPtr decodeDataProcImm(ExtMachInst machInst);
45 StaticInstPtr decodeBranchExcSys(ExtMachInst machInst);
46 StaticInstPtr decodeLoadsStores(ExtMachInst machInst);
47 StaticInstPtr decodeDataProcReg(ExtMachInst machInst);
48
49 template <typename DecoderFeatures>
49 StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst);
50 StaticInstPtr decodeFp(ExtMachInst machInst);
50 StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst);
51 StaticInstPtr decodeFp(ExtMachInst machInst);
52 template <typename DecoderFeatures>
51 StaticInstPtr decodeAdvSIMD(ExtMachInst machInst);
52 StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst);
53
54 StaticInstPtr decodeGem5Ops(ExtMachInst machInst);
55}
56}};
57
58output decoder {{

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1273 return new FailUnimplemented("Unhandled Case2", machInst);
1274 }
1275}
1276}};
1277
1278output decoder {{
1279namespace Aarch64
1280{
53 StaticInstPtr decodeAdvSIMD(ExtMachInst machInst);
54 StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst);
55
56 StaticInstPtr decodeGem5Ops(ExtMachInst machInst);
57}
58}};
59
60output decoder {{

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1275 return new FailUnimplemented("Unhandled Case2", machInst);
1276 }
1277}
1278}};
1279
1280output decoder {{
1281namespace Aarch64
1282{
1283 template <typename DecoderFeatures>
1281 StaticInstPtr
1282 decodeAdvSIMD(ExtMachInst machInst)
1283 {
1284 if (bits(machInst, 24) == 1) {
1285 if (bits(machInst, 10) == 0) {
1284 StaticInstPtr
1285 decodeAdvSIMD(ExtMachInst machInst)
1286 {
1287 if (bits(machInst, 24) == 1) {
1288 if (bits(machInst, 10) == 0) {
1286 return decodeNeonIndexedElem(machInst);
1289 return decodeNeonIndexedElem<DecoderFeatures>(machInst);
1287 } else if (bits(machInst, 23) == 1) {
1288 return new Unknown64(machInst);
1289 } else {
1290 if (bits(machInst, 22, 19)) {
1291 return decodeNeonShiftByImm(machInst);
1292 } else {
1293 return decodeNeonModImm(machInst);
1294 }
1295 }
1296 } else if (bits(machInst, 21) == 1) {
1297 if (bits(machInst, 10) == 1) {
1290 } else if (bits(machInst, 23) == 1) {
1291 return new Unknown64(machInst);
1292 } else {
1293 if (bits(machInst, 22, 19)) {
1294 return decodeNeonShiftByImm(machInst);
1295 } else {
1296 return decodeNeonModImm(machInst);
1297 }
1298 }
1299 } else if (bits(machInst, 21) == 1) {
1300 if (bits(machInst, 10) == 1) {
1298 return decodeNeon3Same(machInst);
1301 return decodeNeon3Same<DecoderFeatures>(machInst);
1299 } else if (bits(machInst, 11) == 0) {
1300 return decodeNeon3Diff(machInst);
1301 } else if (bits(machInst, 20, 17) == 0x0) {
1302 return decodeNeon2RegMisc(machInst);
1303 } else if (bits(machInst, 20, 17) == 0x8) {
1304 return decodeNeonAcrossLanes(machInst);
1305 } else {
1306 return new Unknown64(machInst);

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1952 return new FailUnimplemented("Unhandled Case6", machInst);
1953 }
1954}
1955}};
1956
1957output decoder {{
1958namespace Aarch64
1959{
1302 } else if (bits(machInst, 11) == 0) {
1303 return decodeNeon3Diff(machInst);
1304 } else if (bits(machInst, 20, 17) == 0x0) {
1305 return decodeNeon2RegMisc(machInst);
1306 } else if (bits(machInst, 20, 17) == 0x8) {
1307 return decodeNeonAcrossLanes(machInst);
1308 } else {
1309 return new Unknown64(machInst);

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1955 return new FailUnimplemented("Unhandled Case6", machInst);
1956 }
1957}
1958}};
1959
1960output decoder {{
1961namespace Aarch64
1962{
1963 template <typename DecoderFeatures>
1960 StaticInstPtr
1961 decodeFpAdvSIMD(ExtMachInst machInst)
1962 {
1963
1964 if (bits(machInst, 28) == 0) {
1965 if (bits(machInst, 31) == 0) {
1964 StaticInstPtr
1965 decodeFpAdvSIMD(ExtMachInst machInst)
1966 {
1967
1968 if (bits(machInst, 28) == 0) {
1969 if (bits(machInst, 31) == 0) {
1966 return decodeAdvSIMD(machInst);
1970 return decodeAdvSIMD<DecoderFeatures>(machInst);
1967 } else {
1968 return new Unknown64(machInst);
1969 }
1970 } else if (bits(machInst, 30) == 0) {
1971 return decodeFp(machInst);
1972 } else if (bits(machInst, 31) == 0) {
1973 return decodeAdvSIMDScalar(machInst);
1974 } else {
1975 return new Unknown64(machInst);
1976 }
1977 }
1978}
1979}};
1980
1971 } else {
1972 return new Unknown64(machInst);
1973 }
1974 } else if (bits(machInst, 30) == 0) {
1975 return decodeFp(machInst);
1976 } else if (bits(machInst, 31) == 0) {
1977 return decodeAdvSIMDScalar(machInst);
1978 } else {
1979 return new Unknown64(machInst);
1980 }
1981 }
1982}
1983}};
1984
1985let {{
1986 decoder_output ='''
1987namespace Aarch64
1988{'''
1989 for decoderFlavour, type_dict in decoders.iteritems():
1990 decoder_output +='''
1991template StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst);
1992''' % { "df" : decoderFlavour }
1993 decoder_output +='''
1994}'''
1995}};
1996
1981output decoder {{
1982namespace Aarch64
1983{
1984 StaticInstPtr
1985 decodeGem5Ops(ExtMachInst machInst)
1986 {
1987 const uint32_t m5func = bits(machInst, 23, 16);
1988 switch (m5func) {

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2036 } else if (bits(machInst, 26) == 0) {
2037 // bit 27:25=101
2038 return decodeDataProcReg(machInst);
2039 } else if (bits(machInst, 24) == 1 &&
2040 bits(machInst, 31, 28) == 0xF) {
2041 return decodeGem5Ops(machInst);
2042 } else {
2043 // bit 27:25=111
1997output decoder {{
1998namespace Aarch64
1999{
2000 StaticInstPtr
2001 decodeGem5Ops(ExtMachInst machInst)
2002 {
2003 const uint32_t m5func = bits(machInst, 23, 16);
2004 switch (m5func) {

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2052 } else if (bits(machInst, 26) == 0) {
2053 // bit 27:25=101
2054 return decodeDataProcReg(machInst);
2055 } else if (bits(machInst, 24) == 1 &&
2056 bits(machInst, 31, 28) == 0xF) {
2057 return decodeGem5Ops(machInst);
2058 } else {
2059 // bit 27:25=111
2044 return decodeFpAdvSIMD(machInst);
2060 switch(decoderFlavour){
2061 default:
2062 return decodeFpAdvSIMD<GenericDecoder>(machInst);
2063 }
2045 }
2046 }
2047 '''
2048}};
2064 }
2065 }
2066 '''
2067}};