aarch64.isa (10337:85001c018d4c) | aarch64.isa (10506:aa23216161fa) |
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1// Copyright (c) 2011-2014 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 352 unchanged lines hidden (view full) --- 361 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 362 else 363 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 364 } 365 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 366 if (miscReg == MISCREG_DC_ZVA_Xt && !read) 367 return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); 368 | 1// Copyright (c) 2011-2014 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 352 unchanged lines hidden (view full) --- 361 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 362 else 363 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 364 } 365 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 366 if (miscReg == MISCREG_DC_ZVA_Xt && !read) 367 return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); 368 |
369 if (read) 370 return new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); 371 else | 369 if (read) { 370 StaticInstPtr si = new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); 371 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 372 si->setFlag(StaticInst::IsUnverifiable); 373 return si; 374 } else |
372 return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss); 373 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 374 std::string full_mnem = csprintf("%s %s", 375 read ? "mrs" : "msr", miscRegName[miscReg]); 376 return new WarnUnimplemented(read ? "mrs" : "msr", 377 machInst, full_mnem); 378 } else { 379 return new FailUnimplemented(read ? "mrs" : "msr", --- 1666 unchanged lines hidden --- | 375 return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss); 376 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 377 std::string full_mnem = csprintf("%s %s", 378 read ? "mrs" : "msr", miscRegName[miscReg]); 379 return new WarnUnimplemented(read ? "mrs" : "msr", 380 machInst, full_mnem); 381 } else { 382 return new FailUnimplemented(read ? "mrs" : "msr", --- 1666 unchanged lines hidden --- |