aarch64.isa (12531:3141027bd11a) aarch64.isa (12538:001ad6b1e592)
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37// Thomas Grocutt
38// Mbou Eyole
39// Giacomo Gabrielli
40
41output header {{
42namespace Aarch64
43{
44 StaticInstPtr decodeDataProcImm(ExtMachInst machInst);
45 StaticInstPtr decodeBranchExcSys(ExtMachInst machInst);
46 StaticInstPtr decodeLoadsStores(ExtMachInst machInst);
47 StaticInstPtr decodeDataProcReg(ExtMachInst machInst);
48
49 template <typename DecoderFeatures>
50 StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst);
51 StaticInstPtr decodeFp(ExtMachInst machInst);
52 template <typename DecoderFeatures>
53 StaticInstPtr decodeAdvSIMD(ExtMachInst machInst);
54 StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst);
55
56 StaticInstPtr decodeGem5Ops(ExtMachInst machInst);
57}
58}};
59
60output decoder {{
61namespace Aarch64
62{
63 StaticInstPtr
64 decodeDataProcImm(ExtMachInst machInst)
65 {
66 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
67 IntRegIndex rdsp = makeSP(rd);
68 IntRegIndex rdzr = makeZero(rd);
69 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
70 IntRegIndex rnsp = makeSP(rn);
71
72 uint8_t opc = bits(machInst, 30, 29);
73 bool sf = bits(machInst, 31);
74 bool n = bits(machInst, 22);
75 uint8_t immr = bits(machInst, 21, 16);
76 uint8_t imms = bits(machInst, 15, 10);
77 switch (bits(machInst, 25, 23)) {
78 case 0x0:
79 case 0x1:
80 {
81 uint64_t immlo = bits(machInst, 30, 29);
82 uint64_t immhi = bits(machInst, 23, 5);
83 uint64_t imm = (immlo << 0) | (immhi << 2);
84 if (bits(machInst, 31) == 0)
85 return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm));
86 else
87 return new AdrpXImm(machInst, rdzr, INTREG_ZERO,
88 sext<33>(imm << 12));
89 }
90 case 0x2:
91 case 0x3:
92 {
93 uint32_t imm12 = bits(machInst, 21, 10);
94 uint8_t shift = bits(machInst, 23, 22);
95 uint32_t imm;
96 if (shift == 0x0)
97 imm = imm12 << 0;
98 else if (shift == 0x1)
99 imm = imm12 << 12;
100 else
101 return new Unknown64(machInst);
102 switch (opc) {
103 case 0x0:
104 return new AddXImm(machInst, rdsp, rnsp, imm);
105 case 0x1:
106 return new AddXImmCc(machInst, rdzr, rnsp, imm);
107 case 0x2:
108 return new SubXImm(machInst, rdsp, rnsp, imm);
109 case 0x3:
110 return new SubXImmCc(machInst, rdzr, rnsp, imm);
111 }
112 }
113 case 0x4:
114 {
115 if (!sf && n)
116 return new Unknown64(machInst);
117 // len = MSB(n:NOT(imms)), len < 1 is undefined.
118 uint8_t len = 0;
119 if (n) {
120 len = 6;
121 } else if (imms == 0x3f || imms == 0x3e) {
122 return new Unknown64(machInst);
123 } else {
124 len = findMsbSet(imms ^ 0x3f);
125 }
126 // Generate r, s, and size.
127 uint64_t r = bits(immr, len - 1, 0);
128 uint64_t s = bits(imms, len - 1, 0);
129 uint8_t size = 1 << len;
130 if (s == size - 1)
131 return new Unknown64(machInst);
132 // Generate the pattern with s 1s, rotated by r, with size bits.
133 uint64_t pattern = mask(s + 1);
134 if (r) {
135 pattern = (pattern >> r) | (pattern << (size - r));
136 pattern &= mask(size);
137 }
138 uint8_t width = sf ? 64 : 32;
139 // Replicate that to fill up the immediate.
140 for (unsigned i = 1; i < (width / size); i *= 2)
141 pattern |= (pattern << (i * size));
142 uint64_t imm = pattern;
143
144 switch (opc) {
145 case 0x0:
146 return new AndXImm(machInst, rdsp, rn, imm);
147 case 0x1:
148 return new OrrXImm(machInst, rdsp, rn, imm);
149 case 0x2:
150 return new EorXImm(machInst, rdsp, rn, imm);
151 case 0x3:
152 return new AndXImmCc(machInst, rdzr, rn, imm);
153 }
154 }
155 case 0x5:
156 {
157 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
158 IntRegIndex rdzr = makeZero(rd);
159 uint32_t imm16 = bits(machInst, 20, 5);
160 uint32_t hw = bits(machInst, 22, 21);
161 switch (opc) {
162 case 0x0:
163 return new Movn(machInst, rdzr, imm16, hw * 16);
164 case 0x1:
165 return new Unknown64(machInst);
166 case 0x2:
167 return new Movz(machInst, rdzr, imm16, hw * 16);
168 case 0x3:
169 return new Movk(machInst, rdzr, imm16, hw * 16);
170 }
171 }
172 case 0x6:
173 if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5))))
174 return new Unknown64(machInst);
175 switch (opc) {
176 case 0x0:
177 return new Sbfm64(machInst, rdzr, rn, immr, imms);
178 case 0x1:
179 return new Bfm64(machInst, rdzr, rn, immr, imms);
180 case 0x2:
181 return new Ubfm64(machInst, rdzr, rn, immr, imms);
182 case 0x3:
183 return new Unknown64(machInst);
184 }
185 case 0x7:
186 {
187 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
188 if (opc || bits(machInst, 21))
189 return new Unknown64(machInst);
190 else
191 return new Extr64(machInst, rdzr, rn, rm, imms);
192 }
193 }
194 return new FailUnimplemented("Unhandled Case8", machInst);
195 }
196}
197}};
198
199output decoder {{
200namespace Aarch64
201{
202 StaticInstPtr
203 decodeBranchExcSys(ExtMachInst machInst)
204 {
205 switch (bits(machInst, 30, 29)) {
206 case 0x0:
207 {
208 int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2;
209 if (bits(machInst, 31) == 0)
210 return new B64(machInst, imm);
211 else
212 return new Bl64(machInst, imm);
213 }
214 case 0x1:
215 {
216 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
217 if (bits(machInst, 25) == 0) {
218 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
219 if (bits(machInst, 24) == 0)
220 return new Cbz64(machInst, imm, rt);
221 else
222 return new Cbnz64(machInst, imm, rt);
223 } else {
224 uint64_t bitmask = 0x1;
225 bitmask <<= bits(machInst, 23, 19);
226 int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2;
227 if (bits(machInst, 31))
228 bitmask <<= 32;
229 if (bits(machInst, 24) == 0)
230 return new Tbz64(machInst, bitmask, imm, rt);
231 else
232 return new Tbnz64(machInst, bitmask, imm, rt);
233 }
234 }
235 case 0x2:
236 // bit 30:26=10101
237 if (bits(machInst, 31) == 0) {
238 if (bits(machInst, 25, 24) || bits(machInst, 4))
239 return new Unknown64(machInst);
240 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
241 ConditionCode condCode =
242 (ConditionCode)(uint8_t)(bits(machInst, 3, 0));
243 return new BCond64(machInst, imm, condCode);
244 } else if (bits(machInst, 25, 24) == 0x0) {
1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37// Thomas Grocutt
38// Mbou Eyole
39// Giacomo Gabrielli
40
41output header {{
42namespace Aarch64
43{
44 StaticInstPtr decodeDataProcImm(ExtMachInst machInst);
45 StaticInstPtr decodeBranchExcSys(ExtMachInst machInst);
46 StaticInstPtr decodeLoadsStores(ExtMachInst machInst);
47 StaticInstPtr decodeDataProcReg(ExtMachInst machInst);
48
49 template <typename DecoderFeatures>
50 StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst);
51 StaticInstPtr decodeFp(ExtMachInst machInst);
52 template <typename DecoderFeatures>
53 StaticInstPtr decodeAdvSIMD(ExtMachInst machInst);
54 StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst);
55
56 StaticInstPtr decodeGem5Ops(ExtMachInst machInst);
57}
58}};
59
60output decoder {{
61namespace Aarch64
62{
63 StaticInstPtr
64 decodeDataProcImm(ExtMachInst machInst)
65 {
66 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
67 IntRegIndex rdsp = makeSP(rd);
68 IntRegIndex rdzr = makeZero(rd);
69 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
70 IntRegIndex rnsp = makeSP(rn);
71
72 uint8_t opc = bits(machInst, 30, 29);
73 bool sf = bits(machInst, 31);
74 bool n = bits(machInst, 22);
75 uint8_t immr = bits(machInst, 21, 16);
76 uint8_t imms = bits(machInst, 15, 10);
77 switch (bits(machInst, 25, 23)) {
78 case 0x0:
79 case 0x1:
80 {
81 uint64_t immlo = bits(machInst, 30, 29);
82 uint64_t immhi = bits(machInst, 23, 5);
83 uint64_t imm = (immlo << 0) | (immhi << 2);
84 if (bits(machInst, 31) == 0)
85 return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm));
86 else
87 return new AdrpXImm(machInst, rdzr, INTREG_ZERO,
88 sext<33>(imm << 12));
89 }
90 case 0x2:
91 case 0x3:
92 {
93 uint32_t imm12 = bits(machInst, 21, 10);
94 uint8_t shift = bits(machInst, 23, 22);
95 uint32_t imm;
96 if (shift == 0x0)
97 imm = imm12 << 0;
98 else if (shift == 0x1)
99 imm = imm12 << 12;
100 else
101 return new Unknown64(machInst);
102 switch (opc) {
103 case 0x0:
104 return new AddXImm(machInst, rdsp, rnsp, imm);
105 case 0x1:
106 return new AddXImmCc(machInst, rdzr, rnsp, imm);
107 case 0x2:
108 return new SubXImm(machInst, rdsp, rnsp, imm);
109 case 0x3:
110 return new SubXImmCc(machInst, rdzr, rnsp, imm);
111 }
112 }
113 case 0x4:
114 {
115 if (!sf && n)
116 return new Unknown64(machInst);
117 // len = MSB(n:NOT(imms)), len < 1 is undefined.
118 uint8_t len = 0;
119 if (n) {
120 len = 6;
121 } else if (imms == 0x3f || imms == 0x3e) {
122 return new Unknown64(machInst);
123 } else {
124 len = findMsbSet(imms ^ 0x3f);
125 }
126 // Generate r, s, and size.
127 uint64_t r = bits(immr, len - 1, 0);
128 uint64_t s = bits(imms, len - 1, 0);
129 uint8_t size = 1 << len;
130 if (s == size - 1)
131 return new Unknown64(machInst);
132 // Generate the pattern with s 1s, rotated by r, with size bits.
133 uint64_t pattern = mask(s + 1);
134 if (r) {
135 pattern = (pattern >> r) | (pattern << (size - r));
136 pattern &= mask(size);
137 }
138 uint8_t width = sf ? 64 : 32;
139 // Replicate that to fill up the immediate.
140 for (unsigned i = 1; i < (width / size); i *= 2)
141 pattern |= (pattern << (i * size));
142 uint64_t imm = pattern;
143
144 switch (opc) {
145 case 0x0:
146 return new AndXImm(machInst, rdsp, rn, imm);
147 case 0x1:
148 return new OrrXImm(machInst, rdsp, rn, imm);
149 case 0x2:
150 return new EorXImm(machInst, rdsp, rn, imm);
151 case 0x3:
152 return new AndXImmCc(machInst, rdzr, rn, imm);
153 }
154 }
155 case 0x5:
156 {
157 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
158 IntRegIndex rdzr = makeZero(rd);
159 uint32_t imm16 = bits(machInst, 20, 5);
160 uint32_t hw = bits(machInst, 22, 21);
161 switch (opc) {
162 case 0x0:
163 return new Movn(machInst, rdzr, imm16, hw * 16);
164 case 0x1:
165 return new Unknown64(machInst);
166 case 0x2:
167 return new Movz(machInst, rdzr, imm16, hw * 16);
168 case 0x3:
169 return new Movk(machInst, rdzr, imm16, hw * 16);
170 }
171 }
172 case 0x6:
173 if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5))))
174 return new Unknown64(machInst);
175 switch (opc) {
176 case 0x0:
177 return new Sbfm64(machInst, rdzr, rn, immr, imms);
178 case 0x1:
179 return new Bfm64(machInst, rdzr, rn, immr, imms);
180 case 0x2:
181 return new Ubfm64(machInst, rdzr, rn, immr, imms);
182 case 0x3:
183 return new Unknown64(machInst);
184 }
185 case 0x7:
186 {
187 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
188 if (opc || bits(machInst, 21))
189 return new Unknown64(machInst);
190 else
191 return new Extr64(machInst, rdzr, rn, rm, imms);
192 }
193 }
194 return new FailUnimplemented("Unhandled Case8", machInst);
195 }
196}
197}};
198
199output decoder {{
200namespace Aarch64
201{
202 StaticInstPtr
203 decodeBranchExcSys(ExtMachInst machInst)
204 {
205 switch (bits(machInst, 30, 29)) {
206 case 0x0:
207 {
208 int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2;
209 if (bits(machInst, 31) == 0)
210 return new B64(machInst, imm);
211 else
212 return new Bl64(machInst, imm);
213 }
214 case 0x1:
215 {
216 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
217 if (bits(machInst, 25) == 0) {
218 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
219 if (bits(machInst, 24) == 0)
220 return new Cbz64(machInst, imm, rt);
221 else
222 return new Cbnz64(machInst, imm, rt);
223 } else {
224 uint64_t bitmask = 0x1;
225 bitmask <<= bits(machInst, 23, 19);
226 int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2;
227 if (bits(machInst, 31))
228 bitmask <<= 32;
229 if (bits(machInst, 24) == 0)
230 return new Tbz64(machInst, bitmask, imm, rt);
231 else
232 return new Tbnz64(machInst, bitmask, imm, rt);
233 }
234 }
235 case 0x2:
236 // bit 30:26=10101
237 if (bits(machInst, 31) == 0) {
238 if (bits(machInst, 25, 24) || bits(machInst, 4))
239 return new Unknown64(machInst);
240 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
241 ConditionCode condCode =
242 (ConditionCode)(uint8_t)(bits(machInst, 3, 0));
243 return new BCond64(machInst, imm, condCode);
244 } else if (bits(machInst, 25, 24) == 0x0) {
245
245 if (bits(machInst, 4, 2))
246 return new Unknown64(machInst);
246 if (bits(machInst, 4, 2))
247 return new Unknown64(machInst);
248
249 auto imm16 = bits(machInst, 20, 5);
247 uint8_t decVal = (bits(machInst, 1, 0) << 0) |
248 (bits(machInst, 23, 21) << 2);
250 uint8_t decVal = (bits(machInst, 1, 0) << 0) |
251 (bits(machInst, 23, 21) << 2);
252
249 switch (decVal) {
250 case 0x01:
253 switch (decVal) {
254 case 0x01:
251 return new Svc64(machInst);
255 return new Svc64(machInst, imm16);
252 case 0x02:
256 case 0x02:
253 return new Hvc64(machInst);
257 return new Hvc64(machInst, imm16);
254 case 0x03:
258 case 0x03:
255 return new Smc64(machInst);
259 return new Smc64(machInst, imm16);
256 case 0x04:
260 case 0x04:
257 return new Brk64(machInst);
261 return new Brk64(machInst, imm16);
258 case 0x08:
262 case 0x08:
259 return new Hlt64(machInst);
263 return new Hlt64(machInst, imm16);
260 case 0x15:
261 return new FailUnimplemented("dcps1", machInst);
262 case 0x16:
263 return new FailUnimplemented("dcps2", machInst);
264 case 0x17:
265 return new FailUnimplemented("dcps3", machInst);
266 default:
267 return new Unknown64(machInst);
268 }
269 } else if (bits(machInst, 25, 22) == 0x4) {
270 // bit 31:22=1101010100
271 bool l = bits(machInst, 21);
272 uint8_t op0 = bits(machInst, 20, 19);
273 uint8_t op1 = bits(machInst, 18, 16);
274 uint8_t crn = bits(machInst, 15, 12);
275 uint8_t crm = bits(machInst, 11, 8);
276 uint8_t op2 = bits(machInst, 7, 5);
277 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
278 switch (op0) {
279 case 0x0:
280 if (rt != 0x1f || l)
281 return new Unknown64(machInst);
282 if (crn == 0x2 && op1 == 0x3) {
283 switch (op2) {
284 case 0x0:
285 return new NopInst(machInst);
286 case 0x1:
287 return new YieldInst(machInst);
288 case 0x2:
289 return new WfeInst(machInst);
290 case 0x3:
291 return new WfiInst(machInst);
292 case 0x4:
293 return new SevInst(machInst);
294 case 0x5:
295 return new SevlInst(machInst);
296 default:
297 return new Unknown64(machInst);
298 }
299 } else if (crn == 0x3 && op1 == 0x3) {
300 switch (op2) {
301 case 0x2:
302 return new Clrex64(machInst);
303 case 0x4:
304 return new Dsb64(machInst);
305 case 0x5:
306 return new Dmb64(machInst);
307 case 0x6:
308 return new Isb64(machInst);
309 default:
310 return new Unknown64(machInst);
311 }
312 } else if (crn == 0x4) {
313 // MSR immediate
314 switch (op1 << 3 | op2) {
315 case 0x5:
316 // SP
317 return new MsrSP64(machInst,
318 (IntRegIndex) MISCREG_SPSEL,
319 INTREG_ZERO,
320 crm & 0x1);
321 case 0x1e:
322 // DAIFSet
323 return new MsrDAIFSet64(
324 machInst,
325 (IntRegIndex) MISCREG_DAIF,
326 INTREG_ZERO,
327 crm);
328 case 0x1f:
329 // DAIFClr
330 return new MsrDAIFClr64(
331 machInst,
332 (IntRegIndex) MISCREG_DAIF,
333 INTREG_ZERO,
334 crm);
335 default:
336 return new Unknown64(machInst);
337 }
338 } else {
339 return new Unknown64(machInst);
340 }
341 break;
342 case 0x1:
343 case 0x2:
344 case 0x3:
345 {
346 // bit 31:22=1101010100, 20:19=11
347 bool read = l;
348 MiscRegIndex miscReg =
349 decodeAArch64SysReg(op0, op1, crn, crm, op2);
350 if (read) {
351 if ((miscReg == MISCREG_DC_CIVAC_Xt) ||
352 (miscReg == MISCREG_DC_CVAC_Xt) ||
353 (miscReg == MISCREG_DC_IVAC_Xt) ||
354 (miscReg == MISCREG_DC_ZVA_Xt)) {
355 return new Unknown64(machInst);
356 }
357 }
358 // Check for invalid registers
359 if (miscReg == MISCREG_UNKNOWN) {
360 return new Unknown64(machInst);
361 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
362 if (miscReg == MISCREG_NZCV) {
363 if (read)
364 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg);
365 else
366 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt);
367 }
368 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt);
369 if (read) {
370 StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss);
371 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
372 si->setFlag(StaticInst::IsUnverifiable);
373 return si;
374 } else {
375 switch (miscReg) {
376 case MISCREG_DC_ZVA_Xt:
377 return new Dczva(machInst, rt, miscReg, iss);
378 case MISCREG_DC_CVAU_Xt:
379 return new Dccvau(machInst, rt, miscReg, iss);
380 case MISCREG_DC_CVAC_Xt:
381 return new Dccvac(machInst, rt, miscReg, iss);
382 case MISCREG_DC_CIVAC_Xt:
383 return new Dccivac(machInst, rt, miscReg, iss);
384 case MISCREG_DC_IVAC_Xt:
385 return new Dcivac(machInst, rt, miscReg, iss);
386 default:
387 return new Msr64(machInst, miscReg, rt, iss);
388 }
389 }
390 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
391 std::string full_mnem = csprintf("%s %s",
392 read ? "mrs" : "msr", miscRegName[miscReg]);
393 return new WarnUnimplemented(read ? "mrs" : "msr",
394 machInst, full_mnem);
395 } else {
396 return new FailUnimplemented(read ? "mrs" : "msr",
397 machInst,
398 csprintf("%s %s",
399 read ? "mrs" : "msr",
400 miscRegName[miscReg]));
401 }
402 }
403 break;
404 }
405 } else if (bits(machInst, 25) == 0x1) {
406 uint8_t opc = bits(machInst, 24, 21);
407 uint8_t op2 = bits(machInst, 20, 16);
408 uint8_t op3 = bits(machInst, 15, 10);
409 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
410 uint8_t op4 = bits(machInst, 4, 0);
411 if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0)
412 return new Unknown64(machInst);
413 switch (opc) {
414 case 0x0:
415 return new Br64(machInst, rn);
416 case 0x1:
417 return new Blr64(machInst, rn);
418 case 0x2:
419 return new Ret64(machInst, rn);
420 case 0x4:
421 if (rn != 0x1f)
422 return new Unknown64(machInst);
423 return new Eret64(machInst);
424 case 0x5:
425 if (rn != 0x1f)
426 return new Unknown64(machInst);
427 return new FailUnimplemented("dret", machInst);
428 }
429 }
430 default:
431 return new Unknown64(machInst);
432 }
433 return new FailUnimplemented("Unhandled Case7", machInst);
434 }
435}
436}};
437
438output decoder {{
439namespace Aarch64
440{
441 StaticInstPtr
442 decodeLoadsStores(ExtMachInst machInst)
443 {
444 // bit 27,25=10
445 switch (bits(machInst, 29, 28)) {
446 case 0x0:
447 if (bits(machInst, 26) == 0) {
448 if (bits(machInst, 24) != 0)
449 return new Unknown64(machInst);
450 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
451 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
452 IntRegIndex rnsp = makeSP(rn);
453 IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
454 IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
455 uint8_t opc = (bits(machInst, 15) << 0) |
456 (bits(machInst, 23, 21) << 1);
457 uint8_t size = bits(machInst, 31, 30);
458 switch (opc) {
459 case 0x0:
460 switch (size) {
461 case 0x0:
462 return new STXRB64(machInst, rt, rnsp, rs);
463 case 0x1:
464 return new STXRH64(machInst, rt, rnsp, rs);
465 case 0x2:
466 return new STXRW64(machInst, rt, rnsp, rs);
467 case 0x3:
468 return new STXRX64(machInst, rt, rnsp, rs);
469 }
470 case 0x1:
471 switch (size) {
472 case 0x0:
473 return new STLXRB64(machInst, rt, rnsp, rs);
474 case 0x1:
475 return new STLXRH64(machInst, rt, rnsp, rs);
476 case 0x2:
477 return new STLXRW64(machInst, rt, rnsp, rs);
478 case 0x3:
479 return new STLXRX64(machInst, rt, rnsp, rs);
480 }
481 case 0x2:
482 switch (size) {
483 case 0x0:
484 case 0x1:
485 return new Unknown64(machInst);
486 case 0x2:
487 return new STXPW64(machInst, rs, rt, rt2, rnsp);
488 case 0x3:
489 return new STXPX64(machInst, rs, rt, rt2, rnsp);
490 }
491
492 case 0x3:
493 switch (size) {
494 case 0x0:
495 case 0x1:
496 return new Unknown64(machInst);
497 case 0x2:
498 return new STLXPW64(machInst, rs, rt, rt2, rnsp);
499 case 0x3:
500 return new STLXPX64(machInst, rs, rt, rt2, rnsp);
501 }
502
503 case 0x4:
504 switch (size) {
505 case 0x0:
506 return new LDXRB64(machInst, rt, rnsp, rs);
507 case 0x1:
508 return new LDXRH64(machInst, rt, rnsp, rs);
509 case 0x2:
510 return new LDXRW64(machInst, rt, rnsp, rs);
511 case 0x3:
512 return new LDXRX64(machInst, rt, rnsp, rs);
513 }
514 case 0x5:
515 switch (size) {
516 case 0x0:
517 return new LDAXRB64(machInst, rt, rnsp, rs);
518 case 0x1:
519 return new LDAXRH64(machInst, rt, rnsp, rs);
520 case 0x2:
521 return new LDAXRW64(machInst, rt, rnsp, rs);
522 case 0x3:
523 return new LDAXRX64(machInst, rt, rnsp, rs);
524 }
525 case 0x6:
526 switch (size) {
527 case 0x0:
528 case 0x1:
529 return new Unknown64(machInst);
530 case 0x2:
531 return new LDXPW64(machInst, rt, rt2, rnsp);
532 case 0x3:
533 return new LDXPX64(machInst, rt, rt2, rnsp);
534 }
535
536 case 0x7:
537 switch (size) {
538 case 0x0:
539 case 0x1:
540 return new Unknown64(machInst);
541 case 0x2:
542 return new LDAXPW64(machInst, rt, rt2, rnsp);
543 case 0x3:
544 return new LDAXPX64(machInst, rt, rt2, rnsp);
545 }
546
547 case 0x9:
548 switch (size) {
549 case 0x0:
550 return new STLRB64(machInst, rt, rnsp);
551 case 0x1:
552 return new STLRH64(machInst, rt, rnsp);
553 case 0x2:
554 return new STLRW64(machInst, rt, rnsp);
555 case 0x3:
556 return new STLRX64(machInst, rt, rnsp);
557 }
558 case 0xd:
559 switch (size) {
560 case 0x0:
561 return new LDARB64(machInst, rt, rnsp);
562 case 0x1:
563 return new LDARH64(machInst, rt, rnsp);
564 case 0x2:
565 return new LDARW64(machInst, rt, rnsp);
566 case 0x3:
567 return new LDARX64(machInst, rt, rnsp);
568 }
569 default:
570 return new Unknown64(machInst);
571 }
572 } else if (bits(machInst, 31)) {
573 return new Unknown64(machInst);
574 } else {
575 return decodeNeonMem(machInst);
576 }
577 case 0x1:
578 {
579 if (bits(machInst, 24) != 0)
580 return new Unknown64(machInst);
581 uint8_t switchVal = (bits(machInst, 26) << 0) |
582 (bits(machInst, 31, 30) << 1);
583 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
584 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
585 switch (switchVal) {
586 case 0x0:
587 return new LDRWL64_LIT(machInst, rt, imm);
588 case 0x1:
589 return new LDRSFP64_LIT(machInst, rt, imm);
590 case 0x2:
591 return new LDRXL64_LIT(machInst, rt, imm);
592 case 0x3:
593 return new LDRDFP64_LIT(machInst, rt, imm);
594 case 0x4:
595 return new LDRSWL64_LIT(machInst, rt, imm);
596 case 0x5:
597 return new BigFpMemLit("ldr", machInst, rt, imm);
598 case 0x6:
599 return new PRFM64_LIT(machInst, rt, imm);
600 default:
601 return new Unknown64(machInst);
602 }
603 }
604 case 0x2:
605 {
606 uint8_t opc = bits(machInst, 31, 30);
607 if (opc >= 3)
608 return new Unknown64(machInst);
609 uint32_t size = 0;
610 bool fp = bits(machInst, 26);
611 bool load = bits(machInst, 22);
612 if (fp) {
613 size = 4 << opc;
614 } else {
615 if ((opc == 1) && !load)
616 return new Unknown64(machInst);
617 size = (opc == 0 || opc == 1) ? 4 : 8;
618 }
619 uint8_t type = bits(machInst, 24, 23);
620 int64_t imm = sext<7>(bits(machInst, 21, 15)) * size;
621
622 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
623 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
624 IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
625
626 bool noAlloc = (type == 0);
627 bool signExt = !noAlloc && !fp && opc == 1;
628 PairMemOp::AddrMode mode;
629 const char *mnemonic = NULL;
630 switch (type) {
631 case 0x0:
632 case 0x2:
633 mode = PairMemOp::AddrMd_Offset;
634 break;
635 case 0x1:
636 mode = PairMemOp::AddrMd_PostIndex;
637 break;
638 case 0x3:
639 mode = PairMemOp::AddrMd_PreIndex;
640 break;
641 default:
642 return new Unknown64(machInst);
643 }
644 if (load) {
645 if (noAlloc)
646 mnemonic = "ldnp";
647 else if (signExt)
648 mnemonic = "ldpsw";
649 else
650 mnemonic = "ldp";
651 } else {
652 if (noAlloc)
653 mnemonic = "stnp";
654 else
655 mnemonic = "stp";
656 }
657
658 return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc,
659 signExt, false, false, imm, mode, rn, rt, rt2);
660 }
661 // bit 29:27=111, 25=0
662 case 0x3:
663 {
664 uint8_t switchVal = (bits(machInst, 23, 22) << 0) |
665 (bits(machInst, 26) << 2) |
666 (bits(machInst, 31, 30) << 3);
667 if (bits(machInst, 24) == 1) {
668 uint64_t imm12 = bits(machInst, 21, 10);
669 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
670 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
671 IntRegIndex rnsp = makeSP(rn);
672 switch (switchVal) {
673 case 0x00:
674 return new STRB64_IMM(machInst, rt, rnsp, imm12);
675 case 0x01:
676 return new LDRB64_IMM(machInst, rt, rnsp, imm12);
677 case 0x02:
678 return new LDRSBX64_IMM(machInst, rt, rnsp, imm12);
679 case 0x03:
680 return new LDRSBW64_IMM(machInst, rt, rnsp, imm12);
681 case 0x04:
682 return new STRBFP64_IMM(machInst, rt, rnsp, imm12);
683 case 0x05:
684 return new LDRBFP64_IMM(machInst, rt, rnsp, imm12);
685 case 0x06:
686 return new BigFpMemImm("str", machInst, false,
687 rt, rnsp, imm12 << 4);
688 case 0x07:
689 return new BigFpMemImm("ldr", machInst, true,
690 rt, rnsp, imm12 << 4);
691 case 0x08:
692 return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1);
693 case 0x09:
694 return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1);
695 case 0x0a:
696 return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1);
697 case 0x0b:
698 return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1);
699 case 0x0c:
700 return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1);
701 case 0x0d:
702 return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1);
703 case 0x10:
704 return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2);
705 case 0x11:
706 return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2);
707 case 0x12:
708 return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2);
709 case 0x14:
710 return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2);
711 case 0x15:
712 return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2);
713 case 0x18:
714 return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3);
715 case 0x19:
716 return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3);
717 case 0x1a:
718 return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3);
719 case 0x1c:
720 return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3);
721 case 0x1d:
722 return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3);
723 default:
724 return new Unknown64(machInst);
725 }
726 } else if (bits(machInst, 21) == 1) {
727 if (bits(machInst, 11, 10) != 0x2)
728 return new Unknown64(machInst);
729 if (!bits(machInst, 14))
730 return new Unknown64(machInst);
731 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
732 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
733 IntRegIndex rnsp = makeSP(rn);
734 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
735 ArmExtendType type =
736 (ArmExtendType)(uint32_t)bits(machInst, 15, 13);
737 uint8_t s = bits(machInst, 12);
738 switch (switchVal) {
739 case 0x00:
740 return new STRB64_REG(machInst, rt, rnsp, rm, type, 0);
741 case 0x01:
742 return new LDRB64_REG(machInst, rt, rnsp, rm, type, 0);
743 case 0x02:
744 return new LDRSBX64_REG(machInst, rt, rnsp, rm, type, 0);
745 case 0x03:
746 return new LDRSBW64_REG(machInst, rt, rnsp, rm, type, 0);
747 case 0x04:
748 return new STRBFP64_REG(machInst, rt, rnsp, rm, type, 0);
749 case 0x05:
750 return new LDRBFP64_REG(machInst, rt, rnsp, rm, type, 0);
751 case 0x6:
752 return new BigFpMemReg("str", machInst, false,
753 rt, rnsp, rm, type, s * 4);
754 case 0x7:
755 return new BigFpMemReg("ldr", machInst, true,
756 rt, rnsp, rm, type, s * 4);
757 case 0x08:
758 return new STRH64_REG(machInst, rt, rnsp, rm, type, s);
759 case 0x09:
760 return new LDRH64_REG(machInst, rt, rnsp, rm, type, s);
761 case 0x0a:
762 return new LDRSHX64_REG(machInst, rt, rnsp, rm, type, s);
763 case 0x0b:
764 return new LDRSHW64_REG(machInst, rt, rnsp, rm, type, s);
765 case 0x0c:
766 return new STRHFP64_REG(machInst, rt, rnsp, rm, type, s);
767 case 0x0d:
768 return new LDRHFP64_REG(machInst, rt, rnsp, rm, type, s);
769 case 0x10:
770 return new STRW64_REG(machInst, rt, rnsp, rm, type, s * 2);
771 case 0x11:
772 return new LDRW64_REG(machInst, rt, rnsp, rm, type, s * 2);
773 case 0x12:
774 return new LDRSW64_REG(machInst, rt, rnsp, rm, type, s * 2);
775 case 0x14:
776 return new STRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2);
777 case 0x15:
778 return new LDRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2);
779 case 0x18:
780 return new STRX64_REG(machInst, rt, rnsp, rm, type, s * 3);
781 case 0x19:
782 return new LDRX64_REG(machInst, rt, rnsp, rm, type, s * 3);
783 case 0x1a:
784 return new PRFM64_REG(machInst, rt, rnsp, rm, type, s * 3);
785 case 0x1c:
786 return new STRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3);
787 case 0x1d:
788 return new LDRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3);
789 default:
790 return new Unknown64(machInst);
791 }
792 } else {
793 // bit 29:27=111, 25:24=00, 21=0
794 switch (bits(machInst, 11, 10)) {
795 case 0x0:
796 {
797 IntRegIndex rt =
798 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
799 IntRegIndex rn =
800 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
801 IntRegIndex rnsp = makeSP(rn);
802 uint64_t imm = sext<9>(bits(machInst, 20, 12));
803 switch (switchVal) {
804 case 0x00:
805 return new STURB64_IMM(machInst, rt, rnsp, imm);
806 case 0x01:
807 return new LDURB64_IMM(machInst, rt, rnsp, imm);
808 case 0x02:
809 return new LDURSBX64_IMM(machInst, rt, rnsp, imm);
810 case 0x03:
811 return new LDURSBW64_IMM(machInst, rt, rnsp, imm);
812 case 0x04:
813 return new STURBFP64_IMM(machInst, rt, rnsp, imm);
814 case 0x05:
815 return new LDURBFP64_IMM(machInst, rt, rnsp, imm);
816 case 0x06:
817 return new BigFpMemImm("stur", machInst, false,
818 rt, rnsp, imm);
819 case 0x07:
820 return new BigFpMemImm("ldur", machInst, true,
821 rt, rnsp, imm);
822 case 0x08:
823 return new STURH64_IMM(machInst, rt, rnsp, imm);
824 case 0x09:
825 return new LDURH64_IMM(machInst, rt, rnsp, imm);
826 case 0x0a:
827 return new LDURSHX64_IMM(machInst, rt, rnsp, imm);
828 case 0x0b:
829 return new LDURSHW64_IMM(machInst, rt, rnsp, imm);
830 case 0x0c:
831 return new STURHFP64_IMM(machInst, rt, rnsp, imm);
832 case 0x0d:
833 return new LDURHFP64_IMM(machInst, rt, rnsp, imm);
834 case 0x10:
835 return new STURW64_IMM(machInst, rt, rnsp, imm);
836 case 0x11:
837 return new LDURW64_IMM(machInst, rt, rnsp, imm);
838 case 0x12:
839 return new LDURSW64_IMM(machInst, rt, rnsp, imm);
840 case 0x14:
841 return new STURSFP64_IMM(machInst, rt, rnsp, imm);
842 case 0x15:
843 return new LDURSFP64_IMM(machInst, rt, rnsp, imm);
844 case 0x18:
845 return new STURX64_IMM(machInst, rt, rnsp, imm);
846 case 0x19:
847 return new LDURX64_IMM(machInst, rt, rnsp, imm);
848 case 0x1a:
849 return new PRFUM64_IMM(machInst, rt, rnsp, imm);
850 case 0x1c:
851 return new STURDFP64_IMM(machInst, rt, rnsp, imm);
852 case 0x1d:
853 return new LDURDFP64_IMM(machInst, rt, rnsp, imm);
854 default:
855 return new Unknown64(machInst);
856 }
857 }
858 // bit 29:27=111, 25:24=00, 21=0, 11:10=01
859 case 0x1:
860 {
861 IntRegIndex rt =
862 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
863 IntRegIndex rn =
864 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
865 IntRegIndex rnsp = makeSP(rn);
866 uint64_t imm = sext<9>(bits(machInst, 20, 12));
867 switch (switchVal) {
868 case 0x00:
869 return new STRB64_POST(machInst, rt, rnsp, imm);
870 case 0x01:
871 return new LDRB64_POST(machInst, rt, rnsp, imm);
872 case 0x02:
873 return new LDRSBX64_POST(machInst, rt, rnsp, imm);
874 case 0x03:
875 return new LDRSBW64_POST(machInst, rt, rnsp, imm);
876 case 0x04:
877 return new STRBFP64_POST(machInst, rt, rnsp, imm);
878 case 0x05:
879 return new LDRBFP64_POST(machInst, rt, rnsp, imm);
880 case 0x06:
881 return new BigFpMemPost("str", machInst, false,
882 rt, rnsp, imm);
883 case 0x07:
884 return new BigFpMemPost("ldr", machInst, true,
885 rt, rnsp, imm);
886 case 0x08:
887 return new STRH64_POST(machInst, rt, rnsp, imm);
888 case 0x09:
889 return new LDRH64_POST(machInst, rt, rnsp, imm);
890 case 0x0a:
891 return new LDRSHX64_POST(machInst, rt, rnsp, imm);
892 case 0x0b:
893 return new LDRSHW64_POST(machInst, rt, rnsp, imm);
894 case 0x0c:
895 return new STRHFP64_POST(machInst, rt, rnsp, imm);
896 case 0x0d:
897 return new LDRHFP64_POST(machInst, rt, rnsp, imm);
898 case 0x10:
899 return new STRW64_POST(machInst, rt, rnsp, imm);
900 case 0x11:
901 return new LDRW64_POST(machInst, rt, rnsp, imm);
902 case 0x12:
903 return new LDRSW64_POST(machInst, rt, rnsp, imm);
904 case 0x14:
905 return new STRSFP64_POST(machInst, rt, rnsp, imm);
906 case 0x15:
907 return new LDRSFP64_POST(machInst, rt, rnsp, imm);
908 case 0x18:
909 return new STRX64_POST(machInst, rt, rnsp, imm);
910 case 0x19:
911 return new LDRX64_POST(machInst, rt, rnsp, imm);
912 case 0x1c:
913 return new STRDFP64_POST(machInst, rt, rnsp, imm);
914 case 0x1d:
915 return new LDRDFP64_POST(machInst, rt, rnsp, imm);
916 default:
917 return new Unknown64(machInst);
918 }
919 }
920 case 0x2:
921 {
922 IntRegIndex rt =
923 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
924 IntRegIndex rn =
925 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
926 IntRegIndex rnsp = makeSP(rn);
927 uint64_t imm = sext<9>(bits(machInst, 20, 12));
928 switch (switchVal) {
929 case 0x00:
930 return new STTRB64_IMM(machInst, rt, rnsp, imm);
931 case 0x01:
932 return new LDTRB64_IMM(machInst, rt, rnsp, imm);
933 case 0x02:
934 return new LDTRSBX64_IMM(machInst, rt, rnsp, imm);
935 case 0x03:
936 return new LDTRSBW64_IMM(machInst, rt, rnsp, imm);
937 case 0x08:
938 return new STTRH64_IMM(machInst, rt, rnsp, imm);
939 case 0x09:
940 return new LDTRH64_IMM(machInst, rt, rnsp, imm);
941 case 0x0a:
942 return new LDTRSHX64_IMM(machInst, rt, rnsp, imm);
943 case 0x0b:
944 return new LDTRSHW64_IMM(machInst, rt, rnsp, imm);
945 case 0x10:
946 return new STTRW64_IMM(machInst, rt, rnsp, imm);
947 case 0x11:
948 return new LDTRW64_IMM(machInst, rt, rnsp, imm);
949 case 0x12:
950 return new LDTRSW64_IMM(machInst, rt, rnsp, imm);
951 case 0x18:
952 return new STTRX64_IMM(machInst, rt, rnsp, imm);
953 case 0x19:
954 return new LDTRX64_IMM(machInst, rt, rnsp, imm);
955 default:
956 return new Unknown64(machInst);
957 }
958 }
959 case 0x3:
960 {
961 IntRegIndex rt =
962 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
963 IntRegIndex rn =
964 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
965 IntRegIndex rnsp = makeSP(rn);
966 uint64_t imm = sext<9>(bits(machInst, 20, 12));
967 switch (switchVal) {
968 case 0x00:
969 return new STRB64_PRE(machInst, rt, rnsp, imm);
970 case 0x01:
971 return new LDRB64_PRE(machInst, rt, rnsp, imm);
972 case 0x02:
973 return new LDRSBX64_PRE(machInst, rt, rnsp, imm);
974 case 0x03:
975 return new LDRSBW64_PRE(machInst, rt, rnsp, imm);
976 case 0x04:
977 return new STRBFP64_PRE(machInst, rt, rnsp, imm);
978 case 0x05:
979 return new LDRBFP64_PRE(machInst, rt, rnsp, imm);
980 case 0x06:
981 return new BigFpMemPre("str", machInst, false,
982 rt, rnsp, imm);
983 case 0x07:
984 return new BigFpMemPre("ldr", machInst, true,
985 rt, rnsp, imm);
986 case 0x08:
987 return new STRH64_PRE(machInst, rt, rnsp, imm);
988 case 0x09:
989 return new LDRH64_PRE(machInst, rt, rnsp, imm);
990 case 0x0a:
991 return new LDRSHX64_PRE(machInst, rt, rnsp, imm);
992 case 0x0b:
993 return new LDRSHW64_PRE(machInst, rt, rnsp, imm);
994 case 0x0c:
995 return new STRHFP64_PRE(machInst, rt, rnsp, imm);
996 case 0x0d:
997 return new LDRHFP64_PRE(machInst, rt, rnsp, imm);
998 case 0x10:
999 return new STRW64_PRE(machInst, rt, rnsp, imm);
1000 case 0x11:
1001 return new LDRW64_PRE(machInst, rt, rnsp, imm);
1002 case 0x12:
1003 return new LDRSW64_PRE(machInst, rt, rnsp, imm);
1004 case 0x14:
1005 return new STRSFP64_PRE(machInst, rt, rnsp, imm);
1006 case 0x15:
1007 return new LDRSFP64_PRE(machInst, rt, rnsp, imm);
1008 case 0x18:
1009 return new STRX64_PRE(machInst, rt, rnsp, imm);
1010 case 0x19:
1011 return new LDRX64_PRE(machInst, rt, rnsp, imm);
1012 case 0x1c:
1013 return new STRDFP64_PRE(machInst, rt, rnsp, imm);
1014 case 0x1d:
1015 return new LDRDFP64_PRE(machInst, rt, rnsp, imm);
1016 default:
1017 return new Unknown64(machInst);
1018 }
1019 }
1020 }
1021 }
1022 }
1023 }
1024 return new FailUnimplemented("Unhandled Case1", machInst);
1025 }
1026}
1027}};
1028
1029output decoder {{
1030namespace Aarch64
1031{
1032 StaticInstPtr
1033 decodeDataProcReg(ExtMachInst machInst)
1034 {
1035 uint8_t switchVal = (bits(machInst, 28) << 1) |
1036 (bits(machInst, 24) << 0);
1037 switch (switchVal) {
1038 case 0x0:
1039 {
1040 uint8_t switchVal = (bits(machInst, 21) << 0) |
1041 (bits(machInst, 30, 29) << 1);
1042 ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22);
1043 uint8_t imm6 = bits(machInst, 15, 10);
1044 bool sf = bits(machInst, 31);
1045 if (!sf && (imm6 & 0x20))
1046 return new Unknown64(machInst);
1047 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1048 IntRegIndex rdzr = makeZero(rd);
1049 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1050 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1051
1052 switch (switchVal) {
1053 case 0x0:
1054 return new AndXSReg(machInst, rdzr, rn, rm, imm6, type);
1055 case 0x1:
1056 return new BicXSReg(machInst, rdzr, rn, rm, imm6, type);
1057 case 0x2:
1058 return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type);
1059 case 0x3:
1060 return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type);
1061 case 0x4:
1062 return new EorXSReg(machInst, rdzr, rn, rm, imm6, type);
1063 case 0x5:
1064 return new EonXSReg(machInst, rdzr, rn, rm, imm6, type);
1065 case 0x6:
1066 return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1067 case 0x7:
1068 return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1069 }
1070 }
1071 case 0x1:
1072 {
1073 uint8_t switchVal = bits(machInst, 30, 29);
1074 if (bits(machInst, 21) == 0) {
1075 ArmShiftType type =
1076 (ArmShiftType)(uint8_t)bits(machInst, 23, 22);
1077 if (type == ROR)
1078 return new Unknown64(machInst);
1079 uint8_t imm6 = bits(machInst, 15, 10);
1080 if (!bits(machInst, 31) && bits(imm6, 5))
1081 return new Unknown64(machInst);
1082 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1083 IntRegIndex rdzr = makeZero(rd);
1084 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1085 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1086 switch (switchVal) {
1087 case 0x0:
1088 return new AddXSReg(machInst, rdzr, rn, rm, imm6, type);
1089 case 0x1:
1090 return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1091 case 0x2:
1092 return new SubXSReg(machInst, rdzr, rn, rm, imm6, type);
1093 case 0x3:
1094 return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1095 }
1096 } else {
1097 if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4)
1098 return new Unknown64(machInst);
1099 ArmExtendType type =
1100 (ArmExtendType)(uint8_t)bits(machInst, 15, 13);
1101 uint8_t imm3 = bits(machInst, 12, 10);
1102 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1103 IntRegIndex rdsp = makeSP(rd);
1104 IntRegIndex rdzr = makeZero(rd);
1105 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1106 IntRegIndex rnsp = makeSP(rn);
1107 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1108
1109 switch (switchVal) {
1110 case 0x0:
1111 return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3);
1112 case 0x1:
1113 return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
1114 case 0x2:
1115 return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3);
1116 case 0x3:
1117 return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
1118 }
1119 }
1120 }
1121 case 0x2:
1122 {
1123 if (bits(machInst, 21) == 1)
1124 return new Unknown64(machInst);
1125 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1126 IntRegIndex rdzr = makeZero(rd);
1127 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1128 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1129 switch (bits(machInst, 23, 22)) {
1130 case 0x0:
1131 {
1132 if (bits(machInst, 15, 10))
1133 return new Unknown64(machInst);
1134 uint8_t switchVal = bits(machInst, 30, 29);
1135 switch (switchVal) {
1136 case 0x0:
1137 return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL);
1138 case 0x1:
1139 return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
1140 case 0x2:
1141 return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL);
1142 case 0x3:
1143 return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
1144 }
1145 }
1146 case 0x1:
1147 {
1148 if ((bits(machInst, 4) == 1) ||
1149 (bits(machInst, 10) == 1) ||
1150 (bits(machInst, 29) == 0)) {
1151 return new Unknown64(machInst);
1152 }
1153 ConditionCode cond =
1154 (ConditionCode)(uint8_t)bits(machInst, 15, 12);
1155 uint8_t flags = bits(machInst, 3, 0);
1156 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1157 if (bits(machInst, 11) == 0) {
1158 IntRegIndex rm =
1159 (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1160 if (bits(machInst, 30) == 0) {
1161 return new CcmnReg64(machInst, rn, rm, cond, flags);
1162 } else {
1163 return new CcmpReg64(machInst, rn, rm, cond, flags);
1164 }
1165 } else {
1166 uint8_t imm5 = bits(machInst, 20, 16);
1167 if (bits(machInst, 30) == 0) {
1168 return new CcmnImm64(machInst, rn, imm5, cond, flags);
1169 } else {
1170 return new CcmpImm64(machInst, rn, imm5, cond, flags);
1171 }
1172 }
1173 }
1174 case 0x2:
1175 {
1176 if (bits(machInst, 29) == 1 ||
1177 bits(machInst, 11) == 1) {
1178 return new Unknown64(machInst);
1179 }
1180 uint8_t switchVal = (bits(machInst, 10) << 0) |
1181 (bits(machInst, 30) << 1);
1182 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1183 IntRegIndex rdzr = makeZero(rd);
1184 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1185 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1186 ConditionCode cond =
1187 (ConditionCode)(uint8_t)bits(machInst, 15, 12);
1188 switch (switchVal) {
1189 case 0x0:
1190 return new Csel64(machInst, rdzr, rn, rm, cond);
1191 case 0x1:
1192 return new Csinc64(machInst, rdzr, rn, rm, cond);
1193 case 0x2:
1194 return new Csinv64(machInst, rdzr, rn, rm, cond);
1195 case 0x3:
1196 return new Csneg64(machInst, rdzr, rn, rm, cond);
1197 }
1198 }
1199 case 0x3:
1200 if (bits(machInst, 30) == 0) {
1201 if (bits(machInst, 29) != 0)
1202 return new Unknown64(machInst);
1203 uint8_t switchVal = bits(machInst, 15, 10);
1204 switch (switchVal) {
1205 case 0x2:
1206 return new Udiv64(machInst, rdzr, rn, rm);
1207 case 0x3:
1208 return new Sdiv64(machInst, rdzr, rn, rm);
1209 case 0x8:
1210 return new Lslv64(machInst, rdzr, rn, rm);
1211 case 0x9:
1212 return new Lsrv64(machInst, rdzr, rn, rm);
1213 case 0xa:
1214 return new Asrv64(machInst, rdzr, rn, rm);
1215 case 0xb:
1216 return new Rorv64(machInst, rdzr, rn, rm);
1217 case 0x10:
1218 return new Crc32b64(machInst, rdzr, rn, rm);
1219 case 0x11:
1220 return new Crc32h64(machInst, rdzr, rn, rm);
1221 case 0x12:
1222 return new Crc32w64(machInst, rdzr, rn, rm);
1223 case 0x13:
1224 return new Crc32x64(machInst, rdzr, rn, rm);
1225 case 0x14:
1226 return new Crc32cb64(machInst, rdzr, rn, rm);
1227 case 0x15:
1228 return new Crc32ch64(machInst, rdzr, rn, rm);
1229 case 0x16:
1230 return new Crc32cw64(machInst, rdzr, rn, rm);
1231 case 0x17:
1232 return new Crc32cx64(machInst, rdzr, rn, rm);
1233 default:
1234 return new Unknown64(machInst);
1235 }
1236 } else {
1237 if (bits(machInst, 20, 16) != 0 ||
1238 bits(machInst, 29) != 0) {
1239 return new Unknown64(machInst);
1240 }
1241 uint8_t switchVal = bits(machInst, 15, 10);
1242 switch (switchVal) {
1243 case 0x0:
1244 return new Rbit64(machInst, rdzr, rn);
1245 case 0x1:
1246 return new Rev1664(machInst, rdzr, rn);
1247 case 0x2:
1248 if (bits(machInst, 31) == 0)
1249 return new Rev64(machInst, rdzr, rn);
1250 else
1251 return new Rev3264(machInst, rdzr, rn);
1252 case 0x3:
1253 if (bits(machInst, 31) != 1)
1254 return new Unknown64(machInst);
1255 return new Rev64(machInst, rdzr, rn);
1256 case 0x4:
1257 return new Clz64(machInst, rdzr, rn);
1258 case 0x5:
1259 return new Cls64(machInst, rdzr, rn);
1260 }
1261 }
1262 }
1263 }
1264 case 0x3:
1265 {
1266 if (bits(machInst, 30, 29) != 0x0 ||
1267 (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0))
1268 return new Unknown64(machInst);
1269 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1270 IntRegIndex rdzr = makeZero(rd);
1271 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1272 IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
1273 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1274 switch (bits(machInst, 23, 21)) {
1275 case 0x0:
1276 if (bits(machInst, 15) == 0)
1277 return new Madd64(machInst, rdzr, ra, rn, rm);
1278 else
1279 return new Msub64(machInst, rdzr, ra, rn, rm);
1280 case 0x1:
1281 if (bits(machInst, 15) == 0)
1282 return new Smaddl64(machInst, rdzr, ra, rn, rm);
1283 else
1284 return new Smsubl64(machInst, rdzr, ra, rn, rm);
1285 case 0x2:
1286 if (bits(machInst, 15) != 0)
1287 return new Unknown64(machInst);
1288 return new Smulh64(machInst, rdzr, rn, rm);
1289 case 0x5:
1290 if (bits(machInst, 15) == 0)
1291 return new Umaddl64(machInst, rdzr, ra, rn, rm);
1292 else
1293 return new Umsubl64(machInst, rdzr, ra, rn, rm);
1294 case 0x6:
1295 if (bits(machInst, 15) != 0)
1296 return new Unknown64(machInst);
1297 return new Umulh64(machInst, rdzr, rn, rm);
1298 default:
1299 return new Unknown64(machInst);
1300 }
1301 }
1302 }
1303 return new FailUnimplemented("Unhandled Case2", machInst);
1304 }
1305}
1306}};
1307
1308output decoder {{
1309namespace Aarch64
1310{
1311 template <typename DecoderFeatures>
1312 StaticInstPtr
1313 decodeAdvSIMD(ExtMachInst machInst)
1314 {
1315 if (bits(machInst, 24) == 1) {
1316 if (bits(machInst, 10) == 0) {
1317 return decodeNeonIndexedElem<DecoderFeatures>(machInst);
1318 } else if (bits(machInst, 23) == 1) {
1319 return new Unknown64(machInst);
1320 } else {
1321 if (bits(machInst, 22, 19)) {
1322 return decodeNeonShiftByImm(machInst);
1323 } else {
1324 return decodeNeonModImm(machInst);
1325 }
1326 }
1327 } else if (bits(machInst, 21) == 1) {
1328 if (bits(machInst, 10) == 1) {
1329 return decodeNeon3Same<DecoderFeatures>(machInst);
1330 } else if (bits(machInst, 11) == 0) {
1331 return decodeNeon3Diff(machInst);
1332 } else if (bits(machInst, 20, 17) == 0x0) {
1333 return decodeNeon2RegMisc(machInst);
1334 } else if (bits(machInst, 20, 17) == 0x8) {
1335 return decodeNeonAcrossLanes(machInst);
1336 } else {
1337 return new Unknown64(machInst);
1338 }
1339 } else if (bits(machInst, 24) ||
1340 bits(machInst, 21) ||
1341 bits(machInst, 15)) {
1342 return new Unknown64(machInst);
1343 } else if (bits(machInst, 10) == 1) {
1344 if (bits(machInst, 23, 22))
1345 return new Unknown64(machInst);
1346 return decodeNeonCopy(machInst);
1347 } else if (bits(machInst, 29) == 1) {
1348 return decodeNeonExt(machInst);
1349 } else if (bits(machInst, 11) == 1) {
1350 return decodeNeonZipUzpTrn(machInst);
1351 } else if (bits(machInst, 23, 22) == 0x0) {
1352 return decodeNeonTblTbx(machInst);
1353 } else {
1354 return new Unknown64(machInst);
1355 }
1356 return new FailUnimplemented("Unhandled Case3", machInst);
1357 }
1358}
1359}};
1360
1361
1362output decoder {{
1363namespace Aarch64
1364{
1365 StaticInstPtr
1366 // bit 30=0, 28:25=1111
1367 decodeFp(ExtMachInst machInst)
1368 {
1369 if (bits(machInst, 24) == 1) {
1370 if (bits(machInst, 31) || bits(machInst, 29))
1371 return new Unknown64(machInst);
1372 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1373 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1374 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
1375 IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10);
1376 uint8_t switchVal = (bits(machInst, 23, 21) << 1) |
1377 (bits(machInst, 15) << 0);
1378 switch (switchVal) {
1379 case 0x0: // FMADD Sd = Sa + Sn*Sm
1380 return new FMAddS(machInst, rd, rn, rm, ra);
1381 case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm
1382 return new FMSubS(machInst, rd, rn, rm, ra);
1383 case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm
1384 return new FNMAddS(machInst, rd, rn, rm, ra);
1385 case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm
1386 return new FNMSubS(machInst, rd, rn, rm, ra);
1387 case 0x4: // FMADD Dd = Da + Dn*Dm
1388 return new FMAddD(machInst, rd, rn, rm, ra);
1389 case 0x5: // FMSUB Dd = Da + (-Dn)*Dm
1390 return new FMSubD(machInst, rd, rn, rm, ra);
1391 case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm
1392 return new FNMAddD(machInst, rd, rn, rm, ra);
1393 case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm
1394 return new FNMSubD(machInst, rd, rn, rm, ra);
1395 default:
1396 return new Unknown64(machInst);
1397 }
1398 } else if (bits(machInst, 21) == 0) {
1399 bool s = bits(machInst, 29);
1400 if (s)
1401 return new Unknown64(machInst);
1402 uint8_t switchVal = bits(machInst, 20, 16);
1403 uint8_t type = bits(machInst, 23, 22);
1404 uint8_t scale = bits(machInst, 15, 10);
1405 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1406 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1407 if (bits(machInst, 18, 17) == 3 && scale != 0)
1408 return new Unknown64(machInst);
1409 // 30:24=0011110, 21=0
1410 switch (switchVal) {
1411 case 0x00:
1412 return new FailUnimplemented("fcvtns", machInst);
1413 case 0x01:
1414 return new FailUnimplemented("fcvtnu", machInst);
1415 case 0x02:
1416 switch ( (bits(machInst, 31) << 2) | type ) {
1417 case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits))
1418 return new FcvtSFixedFpSW(machInst, rd, rn, scale);
1419 case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits))
1420 return new FcvtSFixedFpDW(machInst, rd, rn, scale);
1421 case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits))
1422 return new FcvtSFixedFpSX(machInst, rd, rn, scale);
1423 case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits))
1424 return new FcvtSFixedFpDX(machInst, rd, rn, scale);
1425 default:
1426 return new Unknown64(machInst);
1427 }
1428 case 0x03:
1429 switch ( (bits(machInst, 31) << 2) | type ) {
1430 case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits))
1431 return new FcvtUFixedFpSW(machInst, rd, rn, scale);
1432 case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits))
1433 return new FcvtUFixedFpDW(machInst, rd, rn, scale);
1434 case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits))
1435 return new FcvtUFixedFpSX(machInst, rd, rn, scale);
1436 case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits))
1437 return new FcvtUFixedFpDX(machInst, rd, rn, scale);
1438 default:
1439 return new Unknown64(machInst);
1440 }
1441 case 0x04:
1442 return new FailUnimplemented("fcvtas", machInst);
1443 case 0x05:
1444 return new FailUnimplemented("fcvtau", machInst);
1445 case 0x08:
1446 return new FailUnimplemented("fcvtps", machInst);
1447 case 0x09:
1448 return new FailUnimplemented("fcvtpu", machInst);
1449 case 0x0e:
1450 return new FailUnimplemented("fmov elem. to 64", machInst);
1451 case 0x0f:
1452 return new FailUnimplemented("fmov 64 bit", machInst);
1453 case 0x10:
1454 return new FailUnimplemented("fcvtms", machInst);
1455 case 0x11:
1456 return new FailUnimplemented("fcvtmu", machInst);
1457 case 0x18:
1458 switch ( (bits(machInst, 31) << 2) | type ) {
1459 case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits))
1460 return new FcvtFpSFixedSW(machInst, rd, rn, scale);
1461 case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits))
1462 return new FcvtFpSFixedDW(machInst, rd, rn, scale);
1463 case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits))
1464 return new FcvtFpSFixedSX(machInst, rd, rn, scale);
1465 case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits))
1466 return new FcvtFpSFixedDX(machInst, rd, rn, scale);
1467 default:
1468 return new Unknown64(machInst);
1469 }
1470 case 0x19:
1471 switch ( (bits(machInst, 31) << 2) | type ) {
1472 case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits))
1473 return new FcvtFpUFixedSW(machInst, rd, rn, scale);
1474 case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits))
1475 return new FcvtFpUFixedDW(machInst, rd, rn, scale);
1476 case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits))
1477 return new FcvtFpUFixedSX(machInst, rd, rn, scale);
1478 case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits))
1479 return new FcvtFpUFixedDX(machInst, rd, rn, scale);
1480 default:
1481 return new Unknown64(machInst);
1482 }
1483 }
1484 } else {
1485 // 30=0, 28:24=11110, 21=1
1486 uint8_t type = bits(machInst, 23, 22);
1487 uint8_t imm8 = bits(machInst, 20, 13);
1488 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1489 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1490 switch (bits(machInst, 11, 10)) {
1491 case 0x0:
1492 if (bits(machInst, 12) == 1) {
1493 if (bits(machInst, 31) ||
1494 bits(machInst, 29) ||
1495 bits(machInst, 9, 5)) {
1496 return new Unknown64(machInst);
1497 }
1498 // 31:29=000, 28:24=11110, 21=1, 12:10=100
1499 if (type == 0) {
1500 // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5)
1501 // :imm8<5:0>:Zeros(19)
1502 uint32_t imm = vfp_modified_imm(imm8, false);
1503 return new FmovImmS(machInst, rd, imm);
1504 } else if (type == 1) {
1505 // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8)
1506 // :imm8<5:0>:Zeros(48)
1507 uint64_t imm = vfp_modified_imm(imm8, true);
1508 return new FmovImmD(machInst, rd, imm);
1509 } else {
1510 return new Unknown64(machInst);
1511 }
1512 } else if (bits(machInst, 13) == 1) {
1513 if (bits(machInst, 31) ||
1514 bits(machInst, 29) ||
1515 bits(machInst, 15, 14) ||
1516 bits(machInst, 23) ||
1517 bits(machInst, 2, 0)) {
1518 return new Unknown64(machInst);
1519 }
1520 uint8_t switchVal = (bits(machInst, 4, 3) << 0) |
1521 (bits(machInst, 22) << 2);
1522 IntRegIndex rm = (IntRegIndex)(uint32_t)
1523 bits(machInst, 20, 16);
1524 // 28:23=000111100, 21=1, 15:10=001000, 2:0=000
1525 switch (switchVal) {
1526 case 0x0:
1527 // FCMP flags = compareQuiet(Sn,Sm)
1528 return new FCmpRegS(machInst, rn, rm);
1529 case 0x1:
1530 // FCMP flags = compareQuiet(Sn,0.0)
1531 return new FCmpImmS(machInst, rn, 0);
1532 case 0x2:
1533 // FCMPE flags = compareSignaling(Sn,Sm)
1534 return new FCmpERegS(machInst, rn, rm);
1535 case 0x3:
1536 // FCMPE flags = compareSignaling(Sn,0.0)
1537 return new FCmpEImmS(machInst, rn, 0);
1538 case 0x4:
1539 // FCMP flags = compareQuiet(Dn,Dm)
1540 return new FCmpRegD(machInst, rn, rm);
1541 case 0x5:
1542 // FCMP flags = compareQuiet(Dn,0.0)
1543 return new FCmpImmD(machInst, rn, 0);
1544 case 0x6:
1545 // FCMPE flags = compareSignaling(Dn,Dm)
1546 return new FCmpERegD(machInst, rn, rm);
1547 case 0x7:
1548 // FCMPE flags = compareSignaling(Dn,0.0)
1549 return new FCmpEImmD(machInst, rn, 0);
1550 default:
1551 return new Unknown64(machInst);
1552 }
1553 } else if (bits(machInst, 14) == 1) {
1554 if (bits(machInst, 31) || bits(machInst, 29))
1555 return new Unknown64(machInst);
1556 uint8_t opcode = bits(machInst, 20, 15);
1557 // Bits 31:24=00011110, 21=1, 14:10=10000
1558 switch (opcode) {
1559 case 0x0:
1560 if (type == 0)
1561 // FMOV Sd = Sn
1562 return new FmovRegS(machInst, rd, rn);
1563 else if (type == 1)
1564 // FMOV Dd = Dn
1565 return new FmovRegD(machInst, rd, rn);
1566 break;
1567 case 0x1:
1568 if (type == 0)
1569 // FABS Sd = abs(Sn)
1570 return new FAbsS(machInst, rd, rn);
1571 else if (type == 1)
1572 // FABS Dd = abs(Dn)
1573 return new FAbsD(machInst, rd, rn);
1574 break;
1575 case 0x2:
1576 if (type == 0)
1577 // FNEG Sd = -Sn
1578 return new FNegS(machInst, rd, rn);
1579 else if (type == 1)
1580 // FNEG Dd = -Dn
1581 return new FNegD(machInst, rd, rn);
1582 break;
1583 case 0x3:
1584 if (type == 0)
1585 // FSQRT Sd = sqrt(Sn)
1586 return new FSqrtS(machInst, rd, rn);
1587 else if (type == 1)
1588 // FSQRT Dd = sqrt(Dn)
1589 return new FSqrtD(machInst, rd, rn);
1590 break;
1591 case 0x4:
1592 if (type == 1)
1593 // FCVT Sd = convertFormat(Dn)
1594 return new FcvtFpDFpS(machInst, rd, rn);
1595 else if (type == 3)
1596 // FCVT Sd = convertFormat(Hn)
1597 return new FcvtFpHFpS(machInst, rd, rn);
1598 break;
1599 case 0x5:
1600 if (type == 0)
1601 // FCVT Dd = convertFormat(Sn)
1602 return new FCvtFpSFpD(machInst, rd, rn);
1603 else if (type == 3)
1604 // FCVT Dd = convertFormat(Hn)
1605 return new FcvtFpHFpD(machInst, rd, rn);
1606 break;
1607 case 0x7:
1608 if (type == 0)
1609 // FCVT Hd = convertFormat(Sn)
1610 return new FcvtFpSFpH(machInst, rd, rn);
1611 else if (type == 1)
1612 // FCVT Hd = convertFormat(Dn)
1613 return new FcvtFpDFpH(machInst, rd, rn);
1614 break;
1615 case 0x8:
1616 if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn)
1617 return new FRIntNS(machInst, rd, rn);
1618 else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn)
1619 return new FRIntND(machInst, rd, rn);
1620 break;
1621 case 0x9:
1622 if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn)
1623 return new FRIntPS(machInst, rd, rn);
1624 else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn)
1625 return new FRIntPD(machInst, rd, rn);
1626 break;
1627 case 0xa:
1628 if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn)
1629 return new FRIntMS(machInst, rd, rn);
1630 else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn)
1631 return new FRIntMD(machInst, rd, rn);
1632 break;
1633 case 0xb:
1634 if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn)
1635 return new FRIntZS(machInst, rd, rn);
1636 else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn)
1637 return new FRIntZD(machInst, rd, rn);
1638 break;
1639 case 0xc:
1640 if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn)
1641 return new FRIntAS(machInst, rd, rn);
1642 else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn)
1643 return new FRIntAD(machInst, rd, rn);
1644 break;
1645 case 0xe:
1646 if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn)
1647 return new FRIntXS(machInst, rd, rn);
1648 else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn)
1649 return new FRIntXD(machInst, rd, rn);
1650 break;
1651 case 0xf:
1652 if (type == 0) // FRINTI Sd = roundToIntegral(Sn)
1653 return new FRIntIS(machInst, rd, rn);
1654 else if (type == 1) // FRINTI Dd = roundToIntegral(Dn)
1655 return new FRIntID(machInst, rd, rn);
1656 break;
1657 default:
1658 return new Unknown64(machInst);
1659 }
1660 return new Unknown64(machInst);
1661 } else if (bits(machInst, 15) == 1) {
1662 return new Unknown64(machInst);
1663 } else {
1664 if (bits(machInst, 29))
1665 return new Unknown64(machInst);
1666 uint8_t rmode = bits(machInst, 20, 19);
1667 uint8_t switchVal1 = bits(machInst, 18, 16);
1668 uint8_t switchVal2 = (type << 1) | bits(machInst, 31);
1669 // 30:24=0011110, 21=1, 15:10=000000
1670 switch (switchVal1) {
1671 case 0x0:
1672 switch ((switchVal2 << 2) | rmode) {
1673 case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn)
1674 return new FcvtFpSIntWSN(machInst, rd, rn);
1675 case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn)
1676 return new FcvtFpSIntWSP(machInst, rd, rn);
1677 case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn)
1678 return new FcvtFpSIntWSM(machInst, rd, rn);
1679 case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn)
1680 return new FcvtFpSIntWSZ(machInst, rd, rn);
1681 case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn)
1682 return new FcvtFpSIntXSN(machInst, rd, rn);
1683 case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn)
1684 return new FcvtFpSIntXSP(machInst, rd, rn);
1685 case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn)
1686 return new FcvtFpSIntXSM(machInst, rd, rn);
1687 case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn)
1688 return new FcvtFpSIntXSZ(machInst, rd, rn);
1689 case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn)
1690 return new FcvtFpSIntWDN(machInst, rd, rn);
1691 case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn)
1692 return new FcvtFpSIntWDP(machInst, rd, rn);
1693 case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn)
1694 return new FcvtFpSIntWDM(machInst, rd, rn);
1695 case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn)
1696 return new FcvtFpSIntWDZ(machInst, rd, rn);
1697 case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn)
1698 return new FcvtFpSIntXDN(machInst, rd, rn);
1699 case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn)
1700 return new FcvtFpSIntXDP(machInst, rd, rn);
1701 case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn)
1702 return new FcvtFpSIntXDM(machInst, rd, rn);
1703 case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn)
1704 return new FcvtFpSIntXDZ(machInst, rd, rn);
1705 default:
1706 return new Unknown64(machInst);
1707 }
1708 case 0x1:
1709 switch ((switchVal2 << 2) | rmode) {
1710 case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn)
1711 return new FcvtFpUIntWSN(machInst, rd, rn);
1712 case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn)
1713 return new FcvtFpUIntWSP(machInst, rd, rn);
1714 case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn)
1715 return new FcvtFpUIntWSM(machInst, rd, rn);
1716 case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn)
1717 return new FcvtFpUIntWSZ(machInst, rd, rn);
1718 case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn)
1719 return new FcvtFpUIntXSN(machInst, rd, rn);
1720 case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn)
1721 return new FcvtFpUIntXSP(machInst, rd, rn);
1722 case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn)
1723 return new FcvtFpUIntXSM(machInst, rd, rn);
1724 case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn)
1725 return new FcvtFpUIntXSZ(machInst, rd, rn);
1726 case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn)
1727 return new FcvtFpUIntWDN(machInst, rd, rn);
1728 case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn)
1729 return new FcvtFpUIntWDP(machInst, rd, rn);
1730 case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn)
1731 return new FcvtFpUIntWDM(machInst, rd, rn);
1732 case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn)
1733 return new FcvtFpUIntWDZ(machInst, rd, rn);
1734 case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn)
1735 return new FcvtFpUIntXDN(machInst, rd, rn);
1736 case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn)
1737 return new FcvtFpUIntXDP(machInst, rd, rn);
1738 case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn)
1739 return new FcvtFpUIntXDM(machInst, rd, rn);
1740 case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn)
1741 return new FcvtFpUIntXDZ(machInst, rd, rn);
1742 default:
1743 return new Unknown64(machInst);
1744 }
1745 case 0x2:
1746 if (rmode != 0)
1747 return new Unknown64(machInst);
1748 switch (switchVal2) {
1749 case 0: // SCVTF Sd = convertFromInt(Wn)
1750 return new FcvtWSIntFpS(machInst, rd, rn);
1751 case 1: // SCVTF Sd = convertFromInt(Xn)
1752 return new FcvtXSIntFpS(machInst, rd, rn);
1753 case 2: // SCVTF Dd = convertFromInt(Wn)
1754 return new FcvtWSIntFpD(machInst, rd, rn);
1755 case 3: // SCVTF Dd = convertFromInt(Xn)
1756 return new FcvtXSIntFpD(machInst, rd, rn);
1757 default:
1758 return new Unknown64(machInst);
1759 }
1760 case 0x3:
1761 switch (switchVal2) {
1762 case 0: // UCVTF Sd = convertFromInt(Wn)
1763 return new FcvtWUIntFpS(machInst, rd, rn);
1764 case 1: // UCVTF Sd = convertFromInt(Xn)
1765 return new FcvtXUIntFpS(machInst, rd, rn);
1766 case 2: // UCVTF Dd = convertFromInt(Wn)
1767 return new FcvtWUIntFpD(machInst, rd, rn);
1768 case 3: // UCVTF Dd = convertFromInt(Xn)
1769 return new FcvtXUIntFpD(machInst, rd, rn);
1770 default:
1771 return new Unknown64(machInst);
1772 }
1773 case 0x4:
1774 if (rmode != 0)
1775 return new Unknown64(machInst);
1776 switch (switchVal2) {
1777 case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn)
1778 return new FcvtFpSIntWSA(machInst, rd, rn);
1779 case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn)
1780 return new FcvtFpSIntXSA(machInst, rd, rn);
1781 case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn)
1782 return new FcvtFpSIntWDA(machInst, rd, rn);
1783 case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn)
1784 return new FcvtFpSIntXDA(machInst, rd, rn);
1785 default:
1786 return new Unknown64(machInst);
1787 }
1788 case 0x5:
1789 switch (switchVal2) {
1790 case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn)
1791 return new FcvtFpUIntWSA(machInst, rd, rn);
1792 case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn)
1793 return new FcvtFpUIntXSA(machInst, rd, rn);
1794 case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn)
1795 return new FcvtFpUIntWDA(machInst, rd, rn);
1796 case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn)
1797 return new FcvtFpUIntXDA(machInst, rd, rn);
1798 default:
1799 return new Unknown64(machInst);
1800 }
1801 case 0x06:
1802 switch (switchVal2) {
1803 case 0: // FMOV Wd = Sn
1804 if (rmode != 0)
1805 return new Unknown64(machInst);
1806 return new FmovRegCoreW(machInst, rd, rn);
1807 case 3: // FMOV Xd = Dn
1808 if (rmode != 0)
1809 return new Unknown64(machInst);
1810 return new FmovRegCoreX(machInst, rd, rn);
1811 case 5: // FMOV Xd = Vn<127:64>
1812 if (rmode != 1)
1813 return new Unknown64(machInst);
1814 return new FmovURegCoreX(machInst, rd, rn);
1815 default:
1816 return new Unknown64(machInst);
1817 }
1818 break;
1819 case 0x07:
1820 switch (switchVal2) {
1821 case 0: // FMOV Sd = Wn
1822 if (rmode != 0)
1823 return new Unknown64(machInst);
1824 return new FmovCoreRegW(machInst, rd, rn);
1825 case 3: // FMOV Xd = Dn
1826 if (rmode != 0)
1827 return new Unknown64(machInst);
1828 return new FmovCoreRegX(machInst, rd, rn);
1829 case 5: // FMOV Xd = Vn<127:64>
1830 if (rmode != 1)
1831 return new Unknown64(machInst);
1832 return new FmovUCoreRegX(machInst, rd, rn);
1833 default:
1834 return new Unknown64(machInst);
1835 }
1836 break;
1837 default: // Warning! missing cases in switch statement above, that still need to be added
1838 return new Unknown64(machInst);
1839 }
1840 }
1841 case 0x1:
1842 {
1843 if (bits(machInst, 31) ||
1844 bits(machInst, 29) ||
1845 bits(machInst, 23)) {
1846 return new Unknown64(machInst);
1847 }
1848 IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16);
1849 IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5);
1850 uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0);
1851 ConditionCode cond =
1852 (ConditionCode)(uint8_t)(bits(machInst, 15, 12));
1853 uint8_t switchVal = (bits(machInst, 4) << 0) |
1854 (bits(machInst, 22) << 1);
1855 // 31:23=000111100, 21=1, 11:10=01
1856 switch (switchVal) {
1857 case 0x0:
1858 // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv
1859 return new FCCmpRegS(machInst, rn, rm, cond, imm);
1860 case 0x1:
1861 // FCCMP flags = if cond then compareSignaling(Sn,Sm)
1862 // else #nzcv
1863 return new FCCmpERegS(machInst, rn, rm, cond, imm);
1864 case 0x2:
1865 // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv
1866 return new FCCmpRegD(machInst, rn, rm, cond, imm);
1867 case 0x3:
1868 // FCCMP flags = if cond then compareSignaling(Dn,Dm)
1869 // else #nzcv
1870 return new FCCmpERegD(machInst, rn, rm, cond, imm);
1871 default:
1872 return new Unknown64(machInst);
1873 }
1874 }
1875 case 0x2:
1876 {
1877 if (bits(machInst, 31) ||
1878 bits(machInst, 29) ||
1879 bits(machInst, 23)) {
1880 return new Unknown64(machInst);
1881 }
1882 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1883 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1884 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
1885 uint8_t switchVal = (bits(machInst, 15, 12) << 0) |
1886 (bits(machInst, 22) << 4);
1887 switch (switchVal) {
1888 case 0x00: // FMUL Sd = Sn * Sm
1889 return new FMulS(machInst, rd, rn, rm);
1890 case 0x10: // FMUL Dd = Dn * Dm
1891 return new FMulD(machInst, rd, rn, rm);
1892 case 0x01: // FDIV Sd = Sn / Sm
1893 return new FDivS(machInst, rd, rn, rm);
1894 case 0x11: // FDIV Dd = Dn / Dm
1895 return new FDivD(machInst, rd, rn, rm);
1896 case 0x02: // FADD Sd = Sn + Sm
1897 return new FAddS(machInst, rd, rn, rm);
1898 case 0x12: // FADD Dd = Dn + Dm
1899 return new FAddD(machInst, rd, rn, rm);
1900 case 0x03: // FSUB Sd = Sn - Sm
1901 return new FSubS(machInst, rd, rn, rm);
1902 case 0x13: // FSUB Dd = Dn - Dm
1903 return new FSubD(machInst, rd, rn, rm);
1904 case 0x04: // FMAX Sd = max(Sn, Sm)
1905 return new FMaxS(machInst, rd, rn, rm);
1906 case 0x14: // FMAX Dd = max(Dn, Dm)
1907 return new FMaxD(machInst, rd, rn, rm);
1908 case 0x05: // FMIN Sd = min(Sn, Sm)
1909 return new FMinS(machInst, rd, rn, rm);
1910 case 0x15: // FMIN Dd = min(Dn, Dm)
1911 return new FMinD(machInst, rd, rn, rm);
1912 case 0x06: // FMAXNM Sd = maxNum(Sn, Sm)
1913 return new FMaxNMS(machInst, rd, rn, rm);
1914 case 0x16: // FMAXNM Dd = maxNum(Dn, Dm)
1915 return new FMaxNMD(machInst, rd, rn, rm);
1916 case 0x07: // FMINNM Sd = minNum(Sn, Sm)
1917 return new FMinNMS(machInst, rd, rn, rm);
1918 case 0x17: // FMINNM Dd = minNum(Dn, Dm)
1919 return new FMinNMD(machInst, rd, rn, rm);
1920 case 0x08: // FNMUL Sd = -(Sn * Sm)
1921 return new FNMulS(machInst, rd, rn, rm);
1922 case 0x18: // FNMUL Dd = -(Dn * Dm)
1923 return new FNMulD(machInst, rd, rn, rm);
1924 default:
1925 return new Unknown64(machInst);
1926 }
1927 }
1928 case 0x3:
1929 {
1930 if (bits(machInst, 31) || bits(machInst, 29))
1931 return new Unknown64(machInst);
1932 uint8_t type = bits(machInst, 23, 22);
1933 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1934 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1935 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
1936 ConditionCode cond =
1937 (ConditionCode)(uint8_t)(bits(machInst, 15, 12));
1938 if (type == 0) // FCSEL Sd = if cond then Sn else Sm
1939 return new FCSelS(machInst, rd, rn, rm, cond);
1940 else if (type == 1) // FCSEL Dd = if cond then Dn else Dm
1941 return new FCSelD(machInst, rd, rn, rm, cond);
1942 else
1943 return new Unknown64(machInst);
1944 }
1945 }
1946 }
1947 return new FailUnimplemented("Unhandled Case4", machInst);
1948 }
1949}
1950}};
1951
1952output decoder {{
1953namespace Aarch64
1954{
1955 StaticInstPtr
1956 decodeAdvSIMDScalar(ExtMachInst machInst)
1957 {
1958 if (bits(machInst, 24) == 1) {
1959 if (bits(machInst, 10) == 0) {
1960 return decodeNeonScIndexedElem(machInst);
1961 } else if (bits(machInst, 23) == 0) {
1962 return decodeNeonScShiftByImm(machInst);
1963 }
1964 } else if (bits(machInst, 21) == 1) {
1965 if (bits(machInst, 10) == 1) {
1966 return decodeNeonSc3Same(machInst);
1967 } else if (bits(machInst, 11) == 0) {
1968 return decodeNeonSc3Diff(machInst);
1969 } else if (bits(machInst, 20, 17) == 0x0) {
1970 return decodeNeonSc2RegMisc(machInst);
1971 } else if (bits(machInst, 20, 17) == 0x8) {
1972 return decodeNeonScPwise(machInst);
1973 } else {
1974 return new Unknown64(machInst);
1975 }
1976 } else if (bits(machInst, 23, 22) == 0 &&
1977 bits(machInst, 15) == 0 &&
1978 bits(machInst, 10) == 1) {
1979 return decodeNeonScCopy(machInst);
1980 } else {
1981 return new Unknown64(machInst);
1982 }
1983 return new FailUnimplemented("Unhandled Case6", machInst);
1984 }
1985}
1986}};
1987
1988output decoder {{
1989namespace Aarch64
1990{
1991 template <typename DecoderFeatures>
1992 StaticInstPtr
1993 decodeFpAdvSIMD(ExtMachInst machInst)
1994 {
1995
1996 if (bits(machInst, 28) == 0) {
1997 if (bits(machInst, 31) == 0) {
1998 return decodeAdvSIMD<DecoderFeatures>(machInst);
1999 } else {
2000 return new Unknown64(machInst);
2001 }
2002 } else if (bits(machInst, 30) == 0) {
2003 return decodeFp(machInst);
2004 } else if (bits(machInst, 31) == 0) {
2005 return decodeAdvSIMDScalar(machInst);
2006 } else {
2007 return new Unknown64(machInst);
2008 }
2009 }
2010}
2011}};
2012
2013let {{
2014 decoder_output ='''
2015namespace Aarch64
2016{'''
2017 for decoderFlavour, type_dict in decoders.iteritems():
2018 decoder_output +='''
2019template StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst);
2020''' % { "df" : decoderFlavour }
2021 decoder_output +='''
2022}'''
2023}};
2024
2025output decoder {{
2026namespace Aarch64
2027{
2028 StaticInstPtr
2029 decodeGem5Ops(ExtMachInst machInst)
2030 {
2031 const uint32_t m5func = bits(machInst, 23, 16);
2032 switch (m5func) {
2033 case M5OP_ARM: return new Arm(machInst);
2034 case M5OP_QUIESCE: return new Quiesce(machInst);
2035 case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst);
2036 case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst);
2037 case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst);
2038 case M5OP_RPNS: return new Rpns64(machInst);
2039 case M5OP_WAKE_CPU: return new WakeCPU64(machInst);
2040 case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
2041 case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
2042 case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
2043 case M5OP_EXIT: return new M5exit64(machInst);
2044 case M5OP_FAIL: return new M5fail64(machInst);
2045 case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
2046 case M5OP_INIT_PARAM: return new Initparam64(machInst);
2047 case M5OP_RESET_STATS: return new Resetstats64(machInst);
2048 case M5OP_DUMP_STATS: return new Dumpstats64(machInst);
2049 case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst);
2050 case M5OP_CHECKPOINT: return new M5checkpoint64(machInst);
2051 case M5OP_WRITE_FILE: return new M5writefile64(machInst);
2052 case M5OP_READ_FILE: return new M5readfile64(machInst);
2053 case M5OP_DEBUG_BREAK: return new M5break(machInst);
2054 case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
2055 case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst);
2056 case M5OP_PANIC: return new M5panic(machInst);
2057 case M5OP_WORK_BEGIN: return new M5workbegin64(machInst);
2058 case M5OP_WORK_END: return new M5workend64(machInst);
2059 default: return new Unknown64(machInst);
2060 }
2061 }
2062}
2063}};
2064
2065def format Aarch64() {{
2066 decode_block = '''
2067 {
2068 using namespace Aarch64;
2069 if (bits(machInst, 27) == 0x0) {
2070 if (bits(machInst, 28) == 0x0)
2071 return new Unknown64(machInst);
2072 else if (bits(machInst, 26) == 0)
2073 // bit 28:26=100
2074 return decodeDataProcImm(machInst);
2075 else
2076 // bit 28:26=101
2077 return decodeBranchExcSys(machInst);
2078 } else if (bits(machInst, 25) == 0) {
2079 // bit 27=1, 25=0
2080 return decodeLoadsStores(machInst);
2081 } else if (bits(machInst, 26) == 0) {
2082 // bit 27:25=101
2083 return decodeDataProcReg(machInst);
2084 } else if (bits(machInst, 24) == 1 &&
2085 bits(machInst, 31, 28) == 0xF) {
2086 return decodeGem5Ops(machInst);
2087 } else {
2088 // bit 27:25=111
2089 switch(decoderFlavour){
2090 default:
2091 return decodeFpAdvSIMD<GenericDecoder>(machInst);
2092 }
2093 }
2094 }
2095 '''
2096}};
264 case 0x15:
265 return new FailUnimplemented("dcps1", machInst);
266 case 0x16:
267 return new FailUnimplemented("dcps2", machInst);
268 case 0x17:
269 return new FailUnimplemented("dcps3", machInst);
270 default:
271 return new Unknown64(machInst);
272 }
273 } else if (bits(machInst, 25, 22) == 0x4) {
274 // bit 31:22=1101010100
275 bool l = bits(machInst, 21);
276 uint8_t op0 = bits(machInst, 20, 19);
277 uint8_t op1 = bits(machInst, 18, 16);
278 uint8_t crn = bits(machInst, 15, 12);
279 uint8_t crm = bits(machInst, 11, 8);
280 uint8_t op2 = bits(machInst, 7, 5);
281 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
282 switch (op0) {
283 case 0x0:
284 if (rt != 0x1f || l)
285 return new Unknown64(machInst);
286 if (crn == 0x2 && op1 == 0x3) {
287 switch (op2) {
288 case 0x0:
289 return new NopInst(machInst);
290 case 0x1:
291 return new YieldInst(machInst);
292 case 0x2:
293 return new WfeInst(machInst);
294 case 0x3:
295 return new WfiInst(machInst);
296 case 0x4:
297 return new SevInst(machInst);
298 case 0x5:
299 return new SevlInst(machInst);
300 default:
301 return new Unknown64(machInst);
302 }
303 } else if (crn == 0x3 && op1 == 0x3) {
304 switch (op2) {
305 case 0x2:
306 return new Clrex64(machInst);
307 case 0x4:
308 return new Dsb64(machInst);
309 case 0x5:
310 return new Dmb64(machInst);
311 case 0x6:
312 return new Isb64(machInst);
313 default:
314 return new Unknown64(machInst);
315 }
316 } else if (crn == 0x4) {
317 // MSR immediate
318 switch (op1 << 3 | op2) {
319 case 0x5:
320 // SP
321 return new MsrSP64(machInst,
322 (IntRegIndex) MISCREG_SPSEL,
323 INTREG_ZERO,
324 crm & 0x1);
325 case 0x1e:
326 // DAIFSet
327 return new MsrDAIFSet64(
328 machInst,
329 (IntRegIndex) MISCREG_DAIF,
330 INTREG_ZERO,
331 crm);
332 case 0x1f:
333 // DAIFClr
334 return new MsrDAIFClr64(
335 machInst,
336 (IntRegIndex) MISCREG_DAIF,
337 INTREG_ZERO,
338 crm);
339 default:
340 return new Unknown64(machInst);
341 }
342 } else {
343 return new Unknown64(machInst);
344 }
345 break;
346 case 0x1:
347 case 0x2:
348 case 0x3:
349 {
350 // bit 31:22=1101010100, 20:19=11
351 bool read = l;
352 MiscRegIndex miscReg =
353 decodeAArch64SysReg(op0, op1, crn, crm, op2);
354 if (read) {
355 if ((miscReg == MISCREG_DC_CIVAC_Xt) ||
356 (miscReg == MISCREG_DC_CVAC_Xt) ||
357 (miscReg == MISCREG_DC_IVAC_Xt) ||
358 (miscReg == MISCREG_DC_ZVA_Xt)) {
359 return new Unknown64(machInst);
360 }
361 }
362 // Check for invalid registers
363 if (miscReg == MISCREG_UNKNOWN) {
364 return new Unknown64(machInst);
365 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
366 if (miscReg == MISCREG_NZCV) {
367 if (read)
368 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg);
369 else
370 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt);
371 }
372 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt);
373 if (read) {
374 StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss);
375 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
376 si->setFlag(StaticInst::IsUnverifiable);
377 return si;
378 } else {
379 switch (miscReg) {
380 case MISCREG_DC_ZVA_Xt:
381 return new Dczva(machInst, rt, miscReg, iss);
382 case MISCREG_DC_CVAU_Xt:
383 return new Dccvau(machInst, rt, miscReg, iss);
384 case MISCREG_DC_CVAC_Xt:
385 return new Dccvac(machInst, rt, miscReg, iss);
386 case MISCREG_DC_CIVAC_Xt:
387 return new Dccivac(machInst, rt, miscReg, iss);
388 case MISCREG_DC_IVAC_Xt:
389 return new Dcivac(machInst, rt, miscReg, iss);
390 default:
391 return new Msr64(machInst, miscReg, rt, iss);
392 }
393 }
394 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
395 std::string full_mnem = csprintf("%s %s",
396 read ? "mrs" : "msr", miscRegName[miscReg]);
397 return new WarnUnimplemented(read ? "mrs" : "msr",
398 machInst, full_mnem);
399 } else {
400 return new FailUnimplemented(read ? "mrs" : "msr",
401 machInst,
402 csprintf("%s %s",
403 read ? "mrs" : "msr",
404 miscRegName[miscReg]));
405 }
406 }
407 break;
408 }
409 } else if (bits(machInst, 25) == 0x1) {
410 uint8_t opc = bits(machInst, 24, 21);
411 uint8_t op2 = bits(machInst, 20, 16);
412 uint8_t op3 = bits(machInst, 15, 10);
413 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
414 uint8_t op4 = bits(machInst, 4, 0);
415 if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0)
416 return new Unknown64(machInst);
417 switch (opc) {
418 case 0x0:
419 return new Br64(machInst, rn);
420 case 0x1:
421 return new Blr64(machInst, rn);
422 case 0x2:
423 return new Ret64(machInst, rn);
424 case 0x4:
425 if (rn != 0x1f)
426 return new Unknown64(machInst);
427 return new Eret64(machInst);
428 case 0x5:
429 if (rn != 0x1f)
430 return new Unknown64(machInst);
431 return new FailUnimplemented("dret", machInst);
432 }
433 }
434 default:
435 return new Unknown64(machInst);
436 }
437 return new FailUnimplemented("Unhandled Case7", machInst);
438 }
439}
440}};
441
442output decoder {{
443namespace Aarch64
444{
445 StaticInstPtr
446 decodeLoadsStores(ExtMachInst machInst)
447 {
448 // bit 27,25=10
449 switch (bits(machInst, 29, 28)) {
450 case 0x0:
451 if (bits(machInst, 26) == 0) {
452 if (bits(machInst, 24) != 0)
453 return new Unknown64(machInst);
454 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
455 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
456 IntRegIndex rnsp = makeSP(rn);
457 IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
458 IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
459 uint8_t opc = (bits(machInst, 15) << 0) |
460 (bits(machInst, 23, 21) << 1);
461 uint8_t size = bits(machInst, 31, 30);
462 switch (opc) {
463 case 0x0:
464 switch (size) {
465 case 0x0:
466 return new STXRB64(machInst, rt, rnsp, rs);
467 case 0x1:
468 return new STXRH64(machInst, rt, rnsp, rs);
469 case 0x2:
470 return new STXRW64(machInst, rt, rnsp, rs);
471 case 0x3:
472 return new STXRX64(machInst, rt, rnsp, rs);
473 }
474 case 0x1:
475 switch (size) {
476 case 0x0:
477 return new STLXRB64(machInst, rt, rnsp, rs);
478 case 0x1:
479 return new STLXRH64(machInst, rt, rnsp, rs);
480 case 0x2:
481 return new STLXRW64(machInst, rt, rnsp, rs);
482 case 0x3:
483 return new STLXRX64(machInst, rt, rnsp, rs);
484 }
485 case 0x2:
486 switch (size) {
487 case 0x0:
488 case 0x1:
489 return new Unknown64(machInst);
490 case 0x2:
491 return new STXPW64(machInst, rs, rt, rt2, rnsp);
492 case 0x3:
493 return new STXPX64(machInst, rs, rt, rt2, rnsp);
494 }
495
496 case 0x3:
497 switch (size) {
498 case 0x0:
499 case 0x1:
500 return new Unknown64(machInst);
501 case 0x2:
502 return new STLXPW64(machInst, rs, rt, rt2, rnsp);
503 case 0x3:
504 return new STLXPX64(machInst, rs, rt, rt2, rnsp);
505 }
506
507 case 0x4:
508 switch (size) {
509 case 0x0:
510 return new LDXRB64(machInst, rt, rnsp, rs);
511 case 0x1:
512 return new LDXRH64(machInst, rt, rnsp, rs);
513 case 0x2:
514 return new LDXRW64(machInst, rt, rnsp, rs);
515 case 0x3:
516 return new LDXRX64(machInst, rt, rnsp, rs);
517 }
518 case 0x5:
519 switch (size) {
520 case 0x0:
521 return new LDAXRB64(machInst, rt, rnsp, rs);
522 case 0x1:
523 return new LDAXRH64(machInst, rt, rnsp, rs);
524 case 0x2:
525 return new LDAXRW64(machInst, rt, rnsp, rs);
526 case 0x3:
527 return new LDAXRX64(machInst, rt, rnsp, rs);
528 }
529 case 0x6:
530 switch (size) {
531 case 0x0:
532 case 0x1:
533 return new Unknown64(machInst);
534 case 0x2:
535 return new LDXPW64(machInst, rt, rt2, rnsp);
536 case 0x3:
537 return new LDXPX64(machInst, rt, rt2, rnsp);
538 }
539
540 case 0x7:
541 switch (size) {
542 case 0x0:
543 case 0x1:
544 return new Unknown64(machInst);
545 case 0x2:
546 return new LDAXPW64(machInst, rt, rt2, rnsp);
547 case 0x3:
548 return new LDAXPX64(machInst, rt, rt2, rnsp);
549 }
550
551 case 0x9:
552 switch (size) {
553 case 0x0:
554 return new STLRB64(machInst, rt, rnsp);
555 case 0x1:
556 return new STLRH64(machInst, rt, rnsp);
557 case 0x2:
558 return new STLRW64(machInst, rt, rnsp);
559 case 0x3:
560 return new STLRX64(machInst, rt, rnsp);
561 }
562 case 0xd:
563 switch (size) {
564 case 0x0:
565 return new LDARB64(machInst, rt, rnsp);
566 case 0x1:
567 return new LDARH64(machInst, rt, rnsp);
568 case 0x2:
569 return new LDARW64(machInst, rt, rnsp);
570 case 0x3:
571 return new LDARX64(machInst, rt, rnsp);
572 }
573 default:
574 return new Unknown64(machInst);
575 }
576 } else if (bits(machInst, 31)) {
577 return new Unknown64(machInst);
578 } else {
579 return decodeNeonMem(machInst);
580 }
581 case 0x1:
582 {
583 if (bits(machInst, 24) != 0)
584 return new Unknown64(machInst);
585 uint8_t switchVal = (bits(machInst, 26) << 0) |
586 (bits(machInst, 31, 30) << 1);
587 int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
588 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
589 switch (switchVal) {
590 case 0x0:
591 return new LDRWL64_LIT(machInst, rt, imm);
592 case 0x1:
593 return new LDRSFP64_LIT(machInst, rt, imm);
594 case 0x2:
595 return new LDRXL64_LIT(machInst, rt, imm);
596 case 0x3:
597 return new LDRDFP64_LIT(machInst, rt, imm);
598 case 0x4:
599 return new LDRSWL64_LIT(machInst, rt, imm);
600 case 0x5:
601 return new BigFpMemLit("ldr", machInst, rt, imm);
602 case 0x6:
603 return new PRFM64_LIT(machInst, rt, imm);
604 default:
605 return new Unknown64(machInst);
606 }
607 }
608 case 0x2:
609 {
610 uint8_t opc = bits(machInst, 31, 30);
611 if (opc >= 3)
612 return new Unknown64(machInst);
613 uint32_t size = 0;
614 bool fp = bits(machInst, 26);
615 bool load = bits(machInst, 22);
616 if (fp) {
617 size = 4 << opc;
618 } else {
619 if ((opc == 1) && !load)
620 return new Unknown64(machInst);
621 size = (opc == 0 || opc == 1) ? 4 : 8;
622 }
623 uint8_t type = bits(machInst, 24, 23);
624 int64_t imm = sext<7>(bits(machInst, 21, 15)) * size;
625
626 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
627 IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
628 IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
629
630 bool noAlloc = (type == 0);
631 bool signExt = !noAlloc && !fp && opc == 1;
632 PairMemOp::AddrMode mode;
633 const char *mnemonic = NULL;
634 switch (type) {
635 case 0x0:
636 case 0x2:
637 mode = PairMemOp::AddrMd_Offset;
638 break;
639 case 0x1:
640 mode = PairMemOp::AddrMd_PostIndex;
641 break;
642 case 0x3:
643 mode = PairMemOp::AddrMd_PreIndex;
644 break;
645 default:
646 return new Unknown64(machInst);
647 }
648 if (load) {
649 if (noAlloc)
650 mnemonic = "ldnp";
651 else if (signExt)
652 mnemonic = "ldpsw";
653 else
654 mnemonic = "ldp";
655 } else {
656 if (noAlloc)
657 mnemonic = "stnp";
658 else
659 mnemonic = "stp";
660 }
661
662 return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc,
663 signExt, false, false, imm, mode, rn, rt, rt2);
664 }
665 // bit 29:27=111, 25=0
666 case 0x3:
667 {
668 uint8_t switchVal = (bits(machInst, 23, 22) << 0) |
669 (bits(machInst, 26) << 2) |
670 (bits(machInst, 31, 30) << 3);
671 if (bits(machInst, 24) == 1) {
672 uint64_t imm12 = bits(machInst, 21, 10);
673 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
674 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
675 IntRegIndex rnsp = makeSP(rn);
676 switch (switchVal) {
677 case 0x00:
678 return new STRB64_IMM(machInst, rt, rnsp, imm12);
679 case 0x01:
680 return new LDRB64_IMM(machInst, rt, rnsp, imm12);
681 case 0x02:
682 return new LDRSBX64_IMM(machInst, rt, rnsp, imm12);
683 case 0x03:
684 return new LDRSBW64_IMM(machInst, rt, rnsp, imm12);
685 case 0x04:
686 return new STRBFP64_IMM(machInst, rt, rnsp, imm12);
687 case 0x05:
688 return new LDRBFP64_IMM(machInst, rt, rnsp, imm12);
689 case 0x06:
690 return new BigFpMemImm("str", machInst, false,
691 rt, rnsp, imm12 << 4);
692 case 0x07:
693 return new BigFpMemImm("ldr", machInst, true,
694 rt, rnsp, imm12 << 4);
695 case 0x08:
696 return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1);
697 case 0x09:
698 return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1);
699 case 0x0a:
700 return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1);
701 case 0x0b:
702 return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1);
703 case 0x0c:
704 return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1);
705 case 0x0d:
706 return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1);
707 case 0x10:
708 return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2);
709 case 0x11:
710 return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2);
711 case 0x12:
712 return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2);
713 case 0x14:
714 return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2);
715 case 0x15:
716 return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2);
717 case 0x18:
718 return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3);
719 case 0x19:
720 return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3);
721 case 0x1a:
722 return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3);
723 case 0x1c:
724 return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3);
725 case 0x1d:
726 return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3);
727 default:
728 return new Unknown64(machInst);
729 }
730 } else if (bits(machInst, 21) == 1) {
731 if (bits(machInst, 11, 10) != 0x2)
732 return new Unknown64(machInst);
733 if (!bits(machInst, 14))
734 return new Unknown64(machInst);
735 IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
736 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
737 IntRegIndex rnsp = makeSP(rn);
738 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
739 ArmExtendType type =
740 (ArmExtendType)(uint32_t)bits(machInst, 15, 13);
741 uint8_t s = bits(machInst, 12);
742 switch (switchVal) {
743 case 0x00:
744 return new STRB64_REG(machInst, rt, rnsp, rm, type, 0);
745 case 0x01:
746 return new LDRB64_REG(machInst, rt, rnsp, rm, type, 0);
747 case 0x02:
748 return new LDRSBX64_REG(machInst, rt, rnsp, rm, type, 0);
749 case 0x03:
750 return new LDRSBW64_REG(machInst, rt, rnsp, rm, type, 0);
751 case 0x04:
752 return new STRBFP64_REG(machInst, rt, rnsp, rm, type, 0);
753 case 0x05:
754 return new LDRBFP64_REG(machInst, rt, rnsp, rm, type, 0);
755 case 0x6:
756 return new BigFpMemReg("str", machInst, false,
757 rt, rnsp, rm, type, s * 4);
758 case 0x7:
759 return new BigFpMemReg("ldr", machInst, true,
760 rt, rnsp, rm, type, s * 4);
761 case 0x08:
762 return new STRH64_REG(machInst, rt, rnsp, rm, type, s);
763 case 0x09:
764 return new LDRH64_REG(machInst, rt, rnsp, rm, type, s);
765 case 0x0a:
766 return new LDRSHX64_REG(machInst, rt, rnsp, rm, type, s);
767 case 0x0b:
768 return new LDRSHW64_REG(machInst, rt, rnsp, rm, type, s);
769 case 0x0c:
770 return new STRHFP64_REG(machInst, rt, rnsp, rm, type, s);
771 case 0x0d:
772 return new LDRHFP64_REG(machInst, rt, rnsp, rm, type, s);
773 case 0x10:
774 return new STRW64_REG(machInst, rt, rnsp, rm, type, s * 2);
775 case 0x11:
776 return new LDRW64_REG(machInst, rt, rnsp, rm, type, s * 2);
777 case 0x12:
778 return new LDRSW64_REG(machInst, rt, rnsp, rm, type, s * 2);
779 case 0x14:
780 return new STRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2);
781 case 0x15:
782 return new LDRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2);
783 case 0x18:
784 return new STRX64_REG(machInst, rt, rnsp, rm, type, s * 3);
785 case 0x19:
786 return new LDRX64_REG(machInst, rt, rnsp, rm, type, s * 3);
787 case 0x1a:
788 return new PRFM64_REG(machInst, rt, rnsp, rm, type, s * 3);
789 case 0x1c:
790 return new STRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3);
791 case 0x1d:
792 return new LDRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3);
793 default:
794 return new Unknown64(machInst);
795 }
796 } else {
797 // bit 29:27=111, 25:24=00, 21=0
798 switch (bits(machInst, 11, 10)) {
799 case 0x0:
800 {
801 IntRegIndex rt =
802 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
803 IntRegIndex rn =
804 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
805 IntRegIndex rnsp = makeSP(rn);
806 uint64_t imm = sext<9>(bits(machInst, 20, 12));
807 switch (switchVal) {
808 case 0x00:
809 return new STURB64_IMM(machInst, rt, rnsp, imm);
810 case 0x01:
811 return new LDURB64_IMM(machInst, rt, rnsp, imm);
812 case 0x02:
813 return new LDURSBX64_IMM(machInst, rt, rnsp, imm);
814 case 0x03:
815 return new LDURSBW64_IMM(machInst, rt, rnsp, imm);
816 case 0x04:
817 return new STURBFP64_IMM(machInst, rt, rnsp, imm);
818 case 0x05:
819 return new LDURBFP64_IMM(machInst, rt, rnsp, imm);
820 case 0x06:
821 return new BigFpMemImm("stur", machInst, false,
822 rt, rnsp, imm);
823 case 0x07:
824 return new BigFpMemImm("ldur", machInst, true,
825 rt, rnsp, imm);
826 case 0x08:
827 return new STURH64_IMM(machInst, rt, rnsp, imm);
828 case 0x09:
829 return new LDURH64_IMM(machInst, rt, rnsp, imm);
830 case 0x0a:
831 return new LDURSHX64_IMM(machInst, rt, rnsp, imm);
832 case 0x0b:
833 return new LDURSHW64_IMM(machInst, rt, rnsp, imm);
834 case 0x0c:
835 return new STURHFP64_IMM(machInst, rt, rnsp, imm);
836 case 0x0d:
837 return new LDURHFP64_IMM(machInst, rt, rnsp, imm);
838 case 0x10:
839 return new STURW64_IMM(machInst, rt, rnsp, imm);
840 case 0x11:
841 return new LDURW64_IMM(machInst, rt, rnsp, imm);
842 case 0x12:
843 return new LDURSW64_IMM(machInst, rt, rnsp, imm);
844 case 0x14:
845 return new STURSFP64_IMM(machInst, rt, rnsp, imm);
846 case 0x15:
847 return new LDURSFP64_IMM(machInst, rt, rnsp, imm);
848 case 0x18:
849 return new STURX64_IMM(machInst, rt, rnsp, imm);
850 case 0x19:
851 return new LDURX64_IMM(machInst, rt, rnsp, imm);
852 case 0x1a:
853 return new PRFUM64_IMM(machInst, rt, rnsp, imm);
854 case 0x1c:
855 return new STURDFP64_IMM(machInst, rt, rnsp, imm);
856 case 0x1d:
857 return new LDURDFP64_IMM(machInst, rt, rnsp, imm);
858 default:
859 return new Unknown64(machInst);
860 }
861 }
862 // bit 29:27=111, 25:24=00, 21=0, 11:10=01
863 case 0x1:
864 {
865 IntRegIndex rt =
866 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
867 IntRegIndex rn =
868 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
869 IntRegIndex rnsp = makeSP(rn);
870 uint64_t imm = sext<9>(bits(machInst, 20, 12));
871 switch (switchVal) {
872 case 0x00:
873 return new STRB64_POST(machInst, rt, rnsp, imm);
874 case 0x01:
875 return new LDRB64_POST(machInst, rt, rnsp, imm);
876 case 0x02:
877 return new LDRSBX64_POST(machInst, rt, rnsp, imm);
878 case 0x03:
879 return new LDRSBW64_POST(machInst, rt, rnsp, imm);
880 case 0x04:
881 return new STRBFP64_POST(machInst, rt, rnsp, imm);
882 case 0x05:
883 return new LDRBFP64_POST(machInst, rt, rnsp, imm);
884 case 0x06:
885 return new BigFpMemPost("str", machInst, false,
886 rt, rnsp, imm);
887 case 0x07:
888 return new BigFpMemPost("ldr", machInst, true,
889 rt, rnsp, imm);
890 case 0x08:
891 return new STRH64_POST(machInst, rt, rnsp, imm);
892 case 0x09:
893 return new LDRH64_POST(machInst, rt, rnsp, imm);
894 case 0x0a:
895 return new LDRSHX64_POST(machInst, rt, rnsp, imm);
896 case 0x0b:
897 return new LDRSHW64_POST(machInst, rt, rnsp, imm);
898 case 0x0c:
899 return new STRHFP64_POST(machInst, rt, rnsp, imm);
900 case 0x0d:
901 return new LDRHFP64_POST(machInst, rt, rnsp, imm);
902 case 0x10:
903 return new STRW64_POST(machInst, rt, rnsp, imm);
904 case 0x11:
905 return new LDRW64_POST(machInst, rt, rnsp, imm);
906 case 0x12:
907 return new LDRSW64_POST(machInst, rt, rnsp, imm);
908 case 0x14:
909 return new STRSFP64_POST(machInst, rt, rnsp, imm);
910 case 0x15:
911 return new LDRSFP64_POST(machInst, rt, rnsp, imm);
912 case 0x18:
913 return new STRX64_POST(machInst, rt, rnsp, imm);
914 case 0x19:
915 return new LDRX64_POST(machInst, rt, rnsp, imm);
916 case 0x1c:
917 return new STRDFP64_POST(machInst, rt, rnsp, imm);
918 case 0x1d:
919 return new LDRDFP64_POST(machInst, rt, rnsp, imm);
920 default:
921 return new Unknown64(machInst);
922 }
923 }
924 case 0x2:
925 {
926 IntRegIndex rt =
927 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
928 IntRegIndex rn =
929 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
930 IntRegIndex rnsp = makeSP(rn);
931 uint64_t imm = sext<9>(bits(machInst, 20, 12));
932 switch (switchVal) {
933 case 0x00:
934 return new STTRB64_IMM(machInst, rt, rnsp, imm);
935 case 0x01:
936 return new LDTRB64_IMM(machInst, rt, rnsp, imm);
937 case 0x02:
938 return new LDTRSBX64_IMM(machInst, rt, rnsp, imm);
939 case 0x03:
940 return new LDTRSBW64_IMM(machInst, rt, rnsp, imm);
941 case 0x08:
942 return new STTRH64_IMM(machInst, rt, rnsp, imm);
943 case 0x09:
944 return new LDTRH64_IMM(machInst, rt, rnsp, imm);
945 case 0x0a:
946 return new LDTRSHX64_IMM(machInst, rt, rnsp, imm);
947 case 0x0b:
948 return new LDTRSHW64_IMM(machInst, rt, rnsp, imm);
949 case 0x10:
950 return new STTRW64_IMM(machInst, rt, rnsp, imm);
951 case 0x11:
952 return new LDTRW64_IMM(machInst, rt, rnsp, imm);
953 case 0x12:
954 return new LDTRSW64_IMM(machInst, rt, rnsp, imm);
955 case 0x18:
956 return new STTRX64_IMM(machInst, rt, rnsp, imm);
957 case 0x19:
958 return new LDTRX64_IMM(machInst, rt, rnsp, imm);
959 default:
960 return new Unknown64(machInst);
961 }
962 }
963 case 0x3:
964 {
965 IntRegIndex rt =
966 (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
967 IntRegIndex rn =
968 (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
969 IntRegIndex rnsp = makeSP(rn);
970 uint64_t imm = sext<9>(bits(machInst, 20, 12));
971 switch (switchVal) {
972 case 0x00:
973 return new STRB64_PRE(machInst, rt, rnsp, imm);
974 case 0x01:
975 return new LDRB64_PRE(machInst, rt, rnsp, imm);
976 case 0x02:
977 return new LDRSBX64_PRE(machInst, rt, rnsp, imm);
978 case 0x03:
979 return new LDRSBW64_PRE(machInst, rt, rnsp, imm);
980 case 0x04:
981 return new STRBFP64_PRE(machInst, rt, rnsp, imm);
982 case 0x05:
983 return new LDRBFP64_PRE(machInst, rt, rnsp, imm);
984 case 0x06:
985 return new BigFpMemPre("str", machInst, false,
986 rt, rnsp, imm);
987 case 0x07:
988 return new BigFpMemPre("ldr", machInst, true,
989 rt, rnsp, imm);
990 case 0x08:
991 return new STRH64_PRE(machInst, rt, rnsp, imm);
992 case 0x09:
993 return new LDRH64_PRE(machInst, rt, rnsp, imm);
994 case 0x0a:
995 return new LDRSHX64_PRE(machInst, rt, rnsp, imm);
996 case 0x0b:
997 return new LDRSHW64_PRE(machInst, rt, rnsp, imm);
998 case 0x0c:
999 return new STRHFP64_PRE(machInst, rt, rnsp, imm);
1000 case 0x0d:
1001 return new LDRHFP64_PRE(machInst, rt, rnsp, imm);
1002 case 0x10:
1003 return new STRW64_PRE(machInst, rt, rnsp, imm);
1004 case 0x11:
1005 return new LDRW64_PRE(machInst, rt, rnsp, imm);
1006 case 0x12:
1007 return new LDRSW64_PRE(machInst, rt, rnsp, imm);
1008 case 0x14:
1009 return new STRSFP64_PRE(machInst, rt, rnsp, imm);
1010 case 0x15:
1011 return new LDRSFP64_PRE(machInst, rt, rnsp, imm);
1012 case 0x18:
1013 return new STRX64_PRE(machInst, rt, rnsp, imm);
1014 case 0x19:
1015 return new LDRX64_PRE(machInst, rt, rnsp, imm);
1016 case 0x1c:
1017 return new STRDFP64_PRE(machInst, rt, rnsp, imm);
1018 case 0x1d:
1019 return new LDRDFP64_PRE(machInst, rt, rnsp, imm);
1020 default:
1021 return new Unknown64(machInst);
1022 }
1023 }
1024 }
1025 }
1026 }
1027 }
1028 return new FailUnimplemented("Unhandled Case1", machInst);
1029 }
1030}
1031}};
1032
1033output decoder {{
1034namespace Aarch64
1035{
1036 StaticInstPtr
1037 decodeDataProcReg(ExtMachInst machInst)
1038 {
1039 uint8_t switchVal = (bits(machInst, 28) << 1) |
1040 (bits(machInst, 24) << 0);
1041 switch (switchVal) {
1042 case 0x0:
1043 {
1044 uint8_t switchVal = (bits(machInst, 21) << 0) |
1045 (bits(machInst, 30, 29) << 1);
1046 ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22);
1047 uint8_t imm6 = bits(machInst, 15, 10);
1048 bool sf = bits(machInst, 31);
1049 if (!sf && (imm6 & 0x20))
1050 return new Unknown64(machInst);
1051 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1052 IntRegIndex rdzr = makeZero(rd);
1053 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1054 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1055
1056 switch (switchVal) {
1057 case 0x0:
1058 return new AndXSReg(machInst, rdzr, rn, rm, imm6, type);
1059 case 0x1:
1060 return new BicXSReg(machInst, rdzr, rn, rm, imm6, type);
1061 case 0x2:
1062 return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type);
1063 case 0x3:
1064 return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type);
1065 case 0x4:
1066 return new EorXSReg(machInst, rdzr, rn, rm, imm6, type);
1067 case 0x5:
1068 return new EonXSReg(machInst, rdzr, rn, rm, imm6, type);
1069 case 0x6:
1070 return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1071 case 0x7:
1072 return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1073 }
1074 }
1075 case 0x1:
1076 {
1077 uint8_t switchVal = bits(machInst, 30, 29);
1078 if (bits(machInst, 21) == 0) {
1079 ArmShiftType type =
1080 (ArmShiftType)(uint8_t)bits(machInst, 23, 22);
1081 if (type == ROR)
1082 return new Unknown64(machInst);
1083 uint8_t imm6 = bits(machInst, 15, 10);
1084 if (!bits(machInst, 31) && bits(imm6, 5))
1085 return new Unknown64(machInst);
1086 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1087 IntRegIndex rdzr = makeZero(rd);
1088 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1089 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1090 switch (switchVal) {
1091 case 0x0:
1092 return new AddXSReg(machInst, rdzr, rn, rm, imm6, type);
1093 case 0x1:
1094 return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1095 case 0x2:
1096 return new SubXSReg(machInst, rdzr, rn, rm, imm6, type);
1097 case 0x3:
1098 return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1099 }
1100 } else {
1101 if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4)
1102 return new Unknown64(machInst);
1103 ArmExtendType type =
1104 (ArmExtendType)(uint8_t)bits(machInst, 15, 13);
1105 uint8_t imm3 = bits(machInst, 12, 10);
1106 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1107 IntRegIndex rdsp = makeSP(rd);
1108 IntRegIndex rdzr = makeZero(rd);
1109 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1110 IntRegIndex rnsp = makeSP(rn);
1111 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1112
1113 switch (switchVal) {
1114 case 0x0:
1115 return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3);
1116 case 0x1:
1117 return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
1118 case 0x2:
1119 return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3);
1120 case 0x3:
1121 return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
1122 }
1123 }
1124 }
1125 case 0x2:
1126 {
1127 if (bits(machInst, 21) == 1)
1128 return new Unknown64(machInst);
1129 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1130 IntRegIndex rdzr = makeZero(rd);
1131 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1132 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1133 switch (bits(machInst, 23, 22)) {
1134 case 0x0:
1135 {
1136 if (bits(machInst, 15, 10))
1137 return new Unknown64(machInst);
1138 uint8_t switchVal = bits(machInst, 30, 29);
1139 switch (switchVal) {
1140 case 0x0:
1141 return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL);
1142 case 0x1:
1143 return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
1144 case 0x2:
1145 return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL);
1146 case 0x3:
1147 return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
1148 }
1149 }
1150 case 0x1:
1151 {
1152 if ((bits(machInst, 4) == 1) ||
1153 (bits(machInst, 10) == 1) ||
1154 (bits(machInst, 29) == 0)) {
1155 return new Unknown64(machInst);
1156 }
1157 ConditionCode cond =
1158 (ConditionCode)(uint8_t)bits(machInst, 15, 12);
1159 uint8_t flags = bits(machInst, 3, 0);
1160 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1161 if (bits(machInst, 11) == 0) {
1162 IntRegIndex rm =
1163 (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1164 if (bits(machInst, 30) == 0) {
1165 return new CcmnReg64(machInst, rn, rm, cond, flags);
1166 } else {
1167 return new CcmpReg64(machInst, rn, rm, cond, flags);
1168 }
1169 } else {
1170 uint8_t imm5 = bits(machInst, 20, 16);
1171 if (bits(machInst, 30) == 0) {
1172 return new CcmnImm64(machInst, rn, imm5, cond, flags);
1173 } else {
1174 return new CcmpImm64(machInst, rn, imm5, cond, flags);
1175 }
1176 }
1177 }
1178 case 0x2:
1179 {
1180 if (bits(machInst, 29) == 1 ||
1181 bits(machInst, 11) == 1) {
1182 return new Unknown64(machInst);
1183 }
1184 uint8_t switchVal = (bits(machInst, 10) << 0) |
1185 (bits(machInst, 30) << 1);
1186 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1187 IntRegIndex rdzr = makeZero(rd);
1188 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1189 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1190 ConditionCode cond =
1191 (ConditionCode)(uint8_t)bits(machInst, 15, 12);
1192 switch (switchVal) {
1193 case 0x0:
1194 return new Csel64(machInst, rdzr, rn, rm, cond);
1195 case 0x1:
1196 return new Csinc64(machInst, rdzr, rn, rm, cond);
1197 case 0x2:
1198 return new Csinv64(machInst, rdzr, rn, rm, cond);
1199 case 0x3:
1200 return new Csneg64(machInst, rdzr, rn, rm, cond);
1201 }
1202 }
1203 case 0x3:
1204 if (bits(machInst, 30) == 0) {
1205 if (bits(machInst, 29) != 0)
1206 return new Unknown64(machInst);
1207 uint8_t switchVal = bits(machInst, 15, 10);
1208 switch (switchVal) {
1209 case 0x2:
1210 return new Udiv64(machInst, rdzr, rn, rm);
1211 case 0x3:
1212 return new Sdiv64(machInst, rdzr, rn, rm);
1213 case 0x8:
1214 return new Lslv64(machInst, rdzr, rn, rm);
1215 case 0x9:
1216 return new Lsrv64(machInst, rdzr, rn, rm);
1217 case 0xa:
1218 return new Asrv64(machInst, rdzr, rn, rm);
1219 case 0xb:
1220 return new Rorv64(machInst, rdzr, rn, rm);
1221 case 0x10:
1222 return new Crc32b64(machInst, rdzr, rn, rm);
1223 case 0x11:
1224 return new Crc32h64(machInst, rdzr, rn, rm);
1225 case 0x12:
1226 return new Crc32w64(machInst, rdzr, rn, rm);
1227 case 0x13:
1228 return new Crc32x64(machInst, rdzr, rn, rm);
1229 case 0x14:
1230 return new Crc32cb64(machInst, rdzr, rn, rm);
1231 case 0x15:
1232 return new Crc32ch64(machInst, rdzr, rn, rm);
1233 case 0x16:
1234 return new Crc32cw64(machInst, rdzr, rn, rm);
1235 case 0x17:
1236 return new Crc32cx64(machInst, rdzr, rn, rm);
1237 default:
1238 return new Unknown64(machInst);
1239 }
1240 } else {
1241 if (bits(machInst, 20, 16) != 0 ||
1242 bits(machInst, 29) != 0) {
1243 return new Unknown64(machInst);
1244 }
1245 uint8_t switchVal = bits(machInst, 15, 10);
1246 switch (switchVal) {
1247 case 0x0:
1248 return new Rbit64(machInst, rdzr, rn);
1249 case 0x1:
1250 return new Rev1664(machInst, rdzr, rn);
1251 case 0x2:
1252 if (bits(machInst, 31) == 0)
1253 return new Rev64(machInst, rdzr, rn);
1254 else
1255 return new Rev3264(machInst, rdzr, rn);
1256 case 0x3:
1257 if (bits(machInst, 31) != 1)
1258 return new Unknown64(machInst);
1259 return new Rev64(machInst, rdzr, rn);
1260 case 0x4:
1261 return new Clz64(machInst, rdzr, rn);
1262 case 0x5:
1263 return new Cls64(machInst, rdzr, rn);
1264 }
1265 }
1266 }
1267 }
1268 case 0x3:
1269 {
1270 if (bits(machInst, 30, 29) != 0x0 ||
1271 (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0))
1272 return new Unknown64(machInst);
1273 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
1274 IntRegIndex rdzr = makeZero(rd);
1275 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
1276 IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
1277 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
1278 switch (bits(machInst, 23, 21)) {
1279 case 0x0:
1280 if (bits(machInst, 15) == 0)
1281 return new Madd64(machInst, rdzr, ra, rn, rm);
1282 else
1283 return new Msub64(machInst, rdzr, ra, rn, rm);
1284 case 0x1:
1285 if (bits(machInst, 15) == 0)
1286 return new Smaddl64(machInst, rdzr, ra, rn, rm);
1287 else
1288 return new Smsubl64(machInst, rdzr, ra, rn, rm);
1289 case 0x2:
1290 if (bits(machInst, 15) != 0)
1291 return new Unknown64(machInst);
1292 return new Smulh64(machInst, rdzr, rn, rm);
1293 case 0x5:
1294 if (bits(machInst, 15) == 0)
1295 return new Umaddl64(machInst, rdzr, ra, rn, rm);
1296 else
1297 return new Umsubl64(machInst, rdzr, ra, rn, rm);
1298 case 0x6:
1299 if (bits(machInst, 15) != 0)
1300 return new Unknown64(machInst);
1301 return new Umulh64(machInst, rdzr, rn, rm);
1302 default:
1303 return new Unknown64(machInst);
1304 }
1305 }
1306 }
1307 return new FailUnimplemented("Unhandled Case2", machInst);
1308 }
1309}
1310}};
1311
1312output decoder {{
1313namespace Aarch64
1314{
1315 template <typename DecoderFeatures>
1316 StaticInstPtr
1317 decodeAdvSIMD(ExtMachInst machInst)
1318 {
1319 if (bits(machInst, 24) == 1) {
1320 if (bits(machInst, 10) == 0) {
1321 return decodeNeonIndexedElem<DecoderFeatures>(machInst);
1322 } else if (bits(machInst, 23) == 1) {
1323 return new Unknown64(machInst);
1324 } else {
1325 if (bits(machInst, 22, 19)) {
1326 return decodeNeonShiftByImm(machInst);
1327 } else {
1328 return decodeNeonModImm(machInst);
1329 }
1330 }
1331 } else if (bits(machInst, 21) == 1) {
1332 if (bits(machInst, 10) == 1) {
1333 return decodeNeon3Same<DecoderFeatures>(machInst);
1334 } else if (bits(machInst, 11) == 0) {
1335 return decodeNeon3Diff(machInst);
1336 } else if (bits(machInst, 20, 17) == 0x0) {
1337 return decodeNeon2RegMisc(machInst);
1338 } else if (bits(machInst, 20, 17) == 0x8) {
1339 return decodeNeonAcrossLanes(machInst);
1340 } else {
1341 return new Unknown64(machInst);
1342 }
1343 } else if (bits(machInst, 24) ||
1344 bits(machInst, 21) ||
1345 bits(machInst, 15)) {
1346 return new Unknown64(machInst);
1347 } else if (bits(machInst, 10) == 1) {
1348 if (bits(machInst, 23, 22))
1349 return new Unknown64(machInst);
1350 return decodeNeonCopy(machInst);
1351 } else if (bits(machInst, 29) == 1) {
1352 return decodeNeonExt(machInst);
1353 } else if (bits(machInst, 11) == 1) {
1354 return decodeNeonZipUzpTrn(machInst);
1355 } else if (bits(machInst, 23, 22) == 0x0) {
1356 return decodeNeonTblTbx(machInst);
1357 } else {
1358 return new Unknown64(machInst);
1359 }
1360 return new FailUnimplemented("Unhandled Case3", machInst);
1361 }
1362}
1363}};
1364
1365
1366output decoder {{
1367namespace Aarch64
1368{
1369 StaticInstPtr
1370 // bit 30=0, 28:25=1111
1371 decodeFp(ExtMachInst machInst)
1372 {
1373 if (bits(machInst, 24) == 1) {
1374 if (bits(machInst, 31) || bits(machInst, 29))
1375 return new Unknown64(machInst);
1376 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1377 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1378 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
1379 IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10);
1380 uint8_t switchVal = (bits(machInst, 23, 21) << 1) |
1381 (bits(machInst, 15) << 0);
1382 switch (switchVal) {
1383 case 0x0: // FMADD Sd = Sa + Sn*Sm
1384 return new FMAddS(machInst, rd, rn, rm, ra);
1385 case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm
1386 return new FMSubS(machInst, rd, rn, rm, ra);
1387 case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm
1388 return new FNMAddS(machInst, rd, rn, rm, ra);
1389 case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm
1390 return new FNMSubS(machInst, rd, rn, rm, ra);
1391 case 0x4: // FMADD Dd = Da + Dn*Dm
1392 return new FMAddD(machInst, rd, rn, rm, ra);
1393 case 0x5: // FMSUB Dd = Da + (-Dn)*Dm
1394 return new FMSubD(machInst, rd, rn, rm, ra);
1395 case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm
1396 return new FNMAddD(machInst, rd, rn, rm, ra);
1397 case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm
1398 return new FNMSubD(machInst, rd, rn, rm, ra);
1399 default:
1400 return new Unknown64(machInst);
1401 }
1402 } else if (bits(machInst, 21) == 0) {
1403 bool s = bits(machInst, 29);
1404 if (s)
1405 return new Unknown64(machInst);
1406 uint8_t switchVal = bits(machInst, 20, 16);
1407 uint8_t type = bits(machInst, 23, 22);
1408 uint8_t scale = bits(machInst, 15, 10);
1409 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1410 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1411 if (bits(machInst, 18, 17) == 3 && scale != 0)
1412 return new Unknown64(machInst);
1413 // 30:24=0011110, 21=0
1414 switch (switchVal) {
1415 case 0x00:
1416 return new FailUnimplemented("fcvtns", machInst);
1417 case 0x01:
1418 return new FailUnimplemented("fcvtnu", machInst);
1419 case 0x02:
1420 switch ( (bits(machInst, 31) << 2) | type ) {
1421 case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits))
1422 return new FcvtSFixedFpSW(machInst, rd, rn, scale);
1423 case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits))
1424 return new FcvtSFixedFpDW(machInst, rd, rn, scale);
1425 case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits))
1426 return new FcvtSFixedFpSX(machInst, rd, rn, scale);
1427 case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits))
1428 return new FcvtSFixedFpDX(machInst, rd, rn, scale);
1429 default:
1430 return new Unknown64(machInst);
1431 }
1432 case 0x03:
1433 switch ( (bits(machInst, 31) << 2) | type ) {
1434 case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits))
1435 return new FcvtUFixedFpSW(machInst, rd, rn, scale);
1436 case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits))
1437 return new FcvtUFixedFpDW(machInst, rd, rn, scale);
1438 case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits))
1439 return new FcvtUFixedFpSX(machInst, rd, rn, scale);
1440 case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits))
1441 return new FcvtUFixedFpDX(machInst, rd, rn, scale);
1442 default:
1443 return new Unknown64(machInst);
1444 }
1445 case 0x04:
1446 return new FailUnimplemented("fcvtas", machInst);
1447 case 0x05:
1448 return new FailUnimplemented("fcvtau", machInst);
1449 case 0x08:
1450 return new FailUnimplemented("fcvtps", machInst);
1451 case 0x09:
1452 return new FailUnimplemented("fcvtpu", machInst);
1453 case 0x0e:
1454 return new FailUnimplemented("fmov elem. to 64", machInst);
1455 case 0x0f:
1456 return new FailUnimplemented("fmov 64 bit", machInst);
1457 case 0x10:
1458 return new FailUnimplemented("fcvtms", machInst);
1459 case 0x11:
1460 return new FailUnimplemented("fcvtmu", machInst);
1461 case 0x18:
1462 switch ( (bits(machInst, 31) << 2) | type ) {
1463 case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits))
1464 return new FcvtFpSFixedSW(machInst, rd, rn, scale);
1465 case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits))
1466 return new FcvtFpSFixedDW(machInst, rd, rn, scale);
1467 case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits))
1468 return new FcvtFpSFixedSX(machInst, rd, rn, scale);
1469 case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits))
1470 return new FcvtFpSFixedDX(machInst, rd, rn, scale);
1471 default:
1472 return new Unknown64(machInst);
1473 }
1474 case 0x19:
1475 switch ( (bits(machInst, 31) << 2) | type ) {
1476 case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits))
1477 return new FcvtFpUFixedSW(machInst, rd, rn, scale);
1478 case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits))
1479 return new FcvtFpUFixedDW(machInst, rd, rn, scale);
1480 case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits))
1481 return new FcvtFpUFixedSX(machInst, rd, rn, scale);
1482 case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits))
1483 return new FcvtFpUFixedDX(machInst, rd, rn, scale);
1484 default:
1485 return new Unknown64(machInst);
1486 }
1487 }
1488 } else {
1489 // 30=0, 28:24=11110, 21=1
1490 uint8_t type = bits(machInst, 23, 22);
1491 uint8_t imm8 = bits(machInst, 20, 13);
1492 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1493 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1494 switch (bits(machInst, 11, 10)) {
1495 case 0x0:
1496 if (bits(machInst, 12) == 1) {
1497 if (bits(machInst, 31) ||
1498 bits(machInst, 29) ||
1499 bits(machInst, 9, 5)) {
1500 return new Unknown64(machInst);
1501 }
1502 // 31:29=000, 28:24=11110, 21=1, 12:10=100
1503 if (type == 0) {
1504 // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5)
1505 // :imm8<5:0>:Zeros(19)
1506 uint32_t imm = vfp_modified_imm(imm8, false);
1507 return new FmovImmS(machInst, rd, imm);
1508 } else if (type == 1) {
1509 // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8)
1510 // :imm8<5:0>:Zeros(48)
1511 uint64_t imm = vfp_modified_imm(imm8, true);
1512 return new FmovImmD(machInst, rd, imm);
1513 } else {
1514 return new Unknown64(machInst);
1515 }
1516 } else if (bits(machInst, 13) == 1) {
1517 if (bits(machInst, 31) ||
1518 bits(machInst, 29) ||
1519 bits(machInst, 15, 14) ||
1520 bits(machInst, 23) ||
1521 bits(machInst, 2, 0)) {
1522 return new Unknown64(machInst);
1523 }
1524 uint8_t switchVal = (bits(machInst, 4, 3) << 0) |
1525 (bits(machInst, 22) << 2);
1526 IntRegIndex rm = (IntRegIndex)(uint32_t)
1527 bits(machInst, 20, 16);
1528 // 28:23=000111100, 21=1, 15:10=001000, 2:0=000
1529 switch (switchVal) {
1530 case 0x0:
1531 // FCMP flags = compareQuiet(Sn,Sm)
1532 return new FCmpRegS(machInst, rn, rm);
1533 case 0x1:
1534 // FCMP flags = compareQuiet(Sn,0.0)
1535 return new FCmpImmS(machInst, rn, 0);
1536 case 0x2:
1537 // FCMPE flags = compareSignaling(Sn,Sm)
1538 return new FCmpERegS(machInst, rn, rm);
1539 case 0x3:
1540 // FCMPE flags = compareSignaling(Sn,0.0)
1541 return new FCmpEImmS(machInst, rn, 0);
1542 case 0x4:
1543 // FCMP flags = compareQuiet(Dn,Dm)
1544 return new FCmpRegD(machInst, rn, rm);
1545 case 0x5:
1546 // FCMP flags = compareQuiet(Dn,0.0)
1547 return new FCmpImmD(machInst, rn, 0);
1548 case 0x6:
1549 // FCMPE flags = compareSignaling(Dn,Dm)
1550 return new FCmpERegD(machInst, rn, rm);
1551 case 0x7:
1552 // FCMPE flags = compareSignaling(Dn,0.0)
1553 return new FCmpEImmD(machInst, rn, 0);
1554 default:
1555 return new Unknown64(machInst);
1556 }
1557 } else if (bits(machInst, 14) == 1) {
1558 if (bits(machInst, 31) || bits(machInst, 29))
1559 return new Unknown64(machInst);
1560 uint8_t opcode = bits(machInst, 20, 15);
1561 // Bits 31:24=00011110, 21=1, 14:10=10000
1562 switch (opcode) {
1563 case 0x0:
1564 if (type == 0)
1565 // FMOV Sd = Sn
1566 return new FmovRegS(machInst, rd, rn);
1567 else if (type == 1)
1568 // FMOV Dd = Dn
1569 return new FmovRegD(machInst, rd, rn);
1570 break;
1571 case 0x1:
1572 if (type == 0)
1573 // FABS Sd = abs(Sn)
1574 return new FAbsS(machInst, rd, rn);
1575 else if (type == 1)
1576 // FABS Dd = abs(Dn)
1577 return new FAbsD(machInst, rd, rn);
1578 break;
1579 case 0x2:
1580 if (type == 0)
1581 // FNEG Sd = -Sn
1582 return new FNegS(machInst, rd, rn);
1583 else if (type == 1)
1584 // FNEG Dd = -Dn
1585 return new FNegD(machInst, rd, rn);
1586 break;
1587 case 0x3:
1588 if (type == 0)
1589 // FSQRT Sd = sqrt(Sn)
1590 return new FSqrtS(machInst, rd, rn);
1591 else if (type == 1)
1592 // FSQRT Dd = sqrt(Dn)
1593 return new FSqrtD(machInst, rd, rn);
1594 break;
1595 case 0x4:
1596 if (type == 1)
1597 // FCVT Sd = convertFormat(Dn)
1598 return new FcvtFpDFpS(machInst, rd, rn);
1599 else if (type == 3)
1600 // FCVT Sd = convertFormat(Hn)
1601 return new FcvtFpHFpS(machInst, rd, rn);
1602 break;
1603 case 0x5:
1604 if (type == 0)
1605 // FCVT Dd = convertFormat(Sn)
1606 return new FCvtFpSFpD(machInst, rd, rn);
1607 else if (type == 3)
1608 // FCVT Dd = convertFormat(Hn)
1609 return new FcvtFpHFpD(machInst, rd, rn);
1610 break;
1611 case 0x7:
1612 if (type == 0)
1613 // FCVT Hd = convertFormat(Sn)
1614 return new FcvtFpSFpH(machInst, rd, rn);
1615 else if (type == 1)
1616 // FCVT Hd = convertFormat(Dn)
1617 return new FcvtFpDFpH(machInst, rd, rn);
1618 break;
1619 case 0x8:
1620 if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn)
1621 return new FRIntNS(machInst, rd, rn);
1622 else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn)
1623 return new FRIntND(machInst, rd, rn);
1624 break;
1625 case 0x9:
1626 if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn)
1627 return new FRIntPS(machInst, rd, rn);
1628 else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn)
1629 return new FRIntPD(machInst, rd, rn);
1630 break;
1631 case 0xa:
1632 if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn)
1633 return new FRIntMS(machInst, rd, rn);
1634 else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn)
1635 return new FRIntMD(machInst, rd, rn);
1636 break;
1637 case 0xb:
1638 if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn)
1639 return new FRIntZS(machInst, rd, rn);
1640 else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn)
1641 return new FRIntZD(machInst, rd, rn);
1642 break;
1643 case 0xc:
1644 if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn)
1645 return new FRIntAS(machInst, rd, rn);
1646 else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn)
1647 return new FRIntAD(machInst, rd, rn);
1648 break;
1649 case 0xe:
1650 if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn)
1651 return new FRIntXS(machInst, rd, rn);
1652 else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn)
1653 return new FRIntXD(machInst, rd, rn);
1654 break;
1655 case 0xf:
1656 if (type == 0) // FRINTI Sd = roundToIntegral(Sn)
1657 return new FRIntIS(machInst, rd, rn);
1658 else if (type == 1) // FRINTI Dd = roundToIntegral(Dn)
1659 return new FRIntID(machInst, rd, rn);
1660 break;
1661 default:
1662 return new Unknown64(machInst);
1663 }
1664 return new Unknown64(machInst);
1665 } else if (bits(machInst, 15) == 1) {
1666 return new Unknown64(machInst);
1667 } else {
1668 if (bits(machInst, 29))
1669 return new Unknown64(machInst);
1670 uint8_t rmode = bits(machInst, 20, 19);
1671 uint8_t switchVal1 = bits(machInst, 18, 16);
1672 uint8_t switchVal2 = (type << 1) | bits(machInst, 31);
1673 // 30:24=0011110, 21=1, 15:10=000000
1674 switch (switchVal1) {
1675 case 0x0:
1676 switch ((switchVal2 << 2) | rmode) {
1677 case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn)
1678 return new FcvtFpSIntWSN(machInst, rd, rn);
1679 case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn)
1680 return new FcvtFpSIntWSP(machInst, rd, rn);
1681 case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn)
1682 return new FcvtFpSIntWSM(machInst, rd, rn);
1683 case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn)
1684 return new FcvtFpSIntWSZ(machInst, rd, rn);
1685 case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn)
1686 return new FcvtFpSIntXSN(machInst, rd, rn);
1687 case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn)
1688 return new FcvtFpSIntXSP(machInst, rd, rn);
1689 case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn)
1690 return new FcvtFpSIntXSM(machInst, rd, rn);
1691 case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn)
1692 return new FcvtFpSIntXSZ(machInst, rd, rn);
1693 case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn)
1694 return new FcvtFpSIntWDN(machInst, rd, rn);
1695 case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn)
1696 return new FcvtFpSIntWDP(machInst, rd, rn);
1697 case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn)
1698 return new FcvtFpSIntWDM(machInst, rd, rn);
1699 case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn)
1700 return new FcvtFpSIntWDZ(machInst, rd, rn);
1701 case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn)
1702 return new FcvtFpSIntXDN(machInst, rd, rn);
1703 case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn)
1704 return new FcvtFpSIntXDP(machInst, rd, rn);
1705 case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn)
1706 return new FcvtFpSIntXDM(machInst, rd, rn);
1707 case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn)
1708 return new FcvtFpSIntXDZ(machInst, rd, rn);
1709 default:
1710 return new Unknown64(machInst);
1711 }
1712 case 0x1:
1713 switch ((switchVal2 << 2) | rmode) {
1714 case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn)
1715 return new FcvtFpUIntWSN(machInst, rd, rn);
1716 case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn)
1717 return new FcvtFpUIntWSP(machInst, rd, rn);
1718 case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn)
1719 return new FcvtFpUIntWSM(machInst, rd, rn);
1720 case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn)
1721 return new FcvtFpUIntWSZ(machInst, rd, rn);
1722 case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn)
1723 return new FcvtFpUIntXSN(machInst, rd, rn);
1724 case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn)
1725 return new FcvtFpUIntXSP(machInst, rd, rn);
1726 case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn)
1727 return new FcvtFpUIntXSM(machInst, rd, rn);
1728 case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn)
1729 return new FcvtFpUIntXSZ(machInst, rd, rn);
1730 case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn)
1731 return new FcvtFpUIntWDN(machInst, rd, rn);
1732 case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn)
1733 return new FcvtFpUIntWDP(machInst, rd, rn);
1734 case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn)
1735 return new FcvtFpUIntWDM(machInst, rd, rn);
1736 case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn)
1737 return new FcvtFpUIntWDZ(machInst, rd, rn);
1738 case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn)
1739 return new FcvtFpUIntXDN(machInst, rd, rn);
1740 case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn)
1741 return new FcvtFpUIntXDP(machInst, rd, rn);
1742 case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn)
1743 return new FcvtFpUIntXDM(machInst, rd, rn);
1744 case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn)
1745 return new FcvtFpUIntXDZ(machInst, rd, rn);
1746 default:
1747 return new Unknown64(machInst);
1748 }
1749 case 0x2:
1750 if (rmode != 0)
1751 return new Unknown64(machInst);
1752 switch (switchVal2) {
1753 case 0: // SCVTF Sd = convertFromInt(Wn)
1754 return new FcvtWSIntFpS(machInst, rd, rn);
1755 case 1: // SCVTF Sd = convertFromInt(Xn)
1756 return new FcvtXSIntFpS(machInst, rd, rn);
1757 case 2: // SCVTF Dd = convertFromInt(Wn)
1758 return new FcvtWSIntFpD(machInst, rd, rn);
1759 case 3: // SCVTF Dd = convertFromInt(Xn)
1760 return new FcvtXSIntFpD(machInst, rd, rn);
1761 default:
1762 return new Unknown64(machInst);
1763 }
1764 case 0x3:
1765 switch (switchVal2) {
1766 case 0: // UCVTF Sd = convertFromInt(Wn)
1767 return new FcvtWUIntFpS(machInst, rd, rn);
1768 case 1: // UCVTF Sd = convertFromInt(Xn)
1769 return new FcvtXUIntFpS(machInst, rd, rn);
1770 case 2: // UCVTF Dd = convertFromInt(Wn)
1771 return new FcvtWUIntFpD(machInst, rd, rn);
1772 case 3: // UCVTF Dd = convertFromInt(Xn)
1773 return new FcvtXUIntFpD(machInst, rd, rn);
1774 default:
1775 return new Unknown64(machInst);
1776 }
1777 case 0x4:
1778 if (rmode != 0)
1779 return new Unknown64(machInst);
1780 switch (switchVal2) {
1781 case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn)
1782 return new FcvtFpSIntWSA(machInst, rd, rn);
1783 case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn)
1784 return new FcvtFpSIntXSA(machInst, rd, rn);
1785 case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn)
1786 return new FcvtFpSIntWDA(machInst, rd, rn);
1787 case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn)
1788 return new FcvtFpSIntXDA(machInst, rd, rn);
1789 default:
1790 return new Unknown64(machInst);
1791 }
1792 case 0x5:
1793 switch (switchVal2) {
1794 case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn)
1795 return new FcvtFpUIntWSA(machInst, rd, rn);
1796 case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn)
1797 return new FcvtFpUIntXSA(machInst, rd, rn);
1798 case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn)
1799 return new FcvtFpUIntWDA(machInst, rd, rn);
1800 case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn)
1801 return new FcvtFpUIntXDA(machInst, rd, rn);
1802 default:
1803 return new Unknown64(machInst);
1804 }
1805 case 0x06:
1806 switch (switchVal2) {
1807 case 0: // FMOV Wd = Sn
1808 if (rmode != 0)
1809 return new Unknown64(machInst);
1810 return new FmovRegCoreW(machInst, rd, rn);
1811 case 3: // FMOV Xd = Dn
1812 if (rmode != 0)
1813 return new Unknown64(machInst);
1814 return new FmovRegCoreX(machInst, rd, rn);
1815 case 5: // FMOV Xd = Vn<127:64>
1816 if (rmode != 1)
1817 return new Unknown64(machInst);
1818 return new FmovURegCoreX(machInst, rd, rn);
1819 default:
1820 return new Unknown64(machInst);
1821 }
1822 break;
1823 case 0x07:
1824 switch (switchVal2) {
1825 case 0: // FMOV Sd = Wn
1826 if (rmode != 0)
1827 return new Unknown64(machInst);
1828 return new FmovCoreRegW(machInst, rd, rn);
1829 case 3: // FMOV Xd = Dn
1830 if (rmode != 0)
1831 return new Unknown64(machInst);
1832 return new FmovCoreRegX(machInst, rd, rn);
1833 case 5: // FMOV Xd = Vn<127:64>
1834 if (rmode != 1)
1835 return new Unknown64(machInst);
1836 return new FmovUCoreRegX(machInst, rd, rn);
1837 default:
1838 return new Unknown64(machInst);
1839 }
1840 break;
1841 default: // Warning! missing cases in switch statement above, that still need to be added
1842 return new Unknown64(machInst);
1843 }
1844 }
1845 case 0x1:
1846 {
1847 if (bits(machInst, 31) ||
1848 bits(machInst, 29) ||
1849 bits(machInst, 23)) {
1850 return new Unknown64(machInst);
1851 }
1852 IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16);
1853 IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5);
1854 uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0);
1855 ConditionCode cond =
1856 (ConditionCode)(uint8_t)(bits(machInst, 15, 12));
1857 uint8_t switchVal = (bits(machInst, 4) << 0) |
1858 (bits(machInst, 22) << 1);
1859 // 31:23=000111100, 21=1, 11:10=01
1860 switch (switchVal) {
1861 case 0x0:
1862 // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv
1863 return new FCCmpRegS(machInst, rn, rm, cond, imm);
1864 case 0x1:
1865 // FCCMP flags = if cond then compareSignaling(Sn,Sm)
1866 // else #nzcv
1867 return new FCCmpERegS(machInst, rn, rm, cond, imm);
1868 case 0x2:
1869 // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv
1870 return new FCCmpRegD(machInst, rn, rm, cond, imm);
1871 case 0x3:
1872 // FCCMP flags = if cond then compareSignaling(Dn,Dm)
1873 // else #nzcv
1874 return new FCCmpERegD(machInst, rn, rm, cond, imm);
1875 default:
1876 return new Unknown64(machInst);
1877 }
1878 }
1879 case 0x2:
1880 {
1881 if (bits(machInst, 31) ||
1882 bits(machInst, 29) ||
1883 bits(machInst, 23)) {
1884 return new Unknown64(machInst);
1885 }
1886 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1887 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1888 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
1889 uint8_t switchVal = (bits(machInst, 15, 12) << 0) |
1890 (bits(machInst, 22) << 4);
1891 switch (switchVal) {
1892 case 0x00: // FMUL Sd = Sn * Sm
1893 return new FMulS(machInst, rd, rn, rm);
1894 case 0x10: // FMUL Dd = Dn * Dm
1895 return new FMulD(machInst, rd, rn, rm);
1896 case 0x01: // FDIV Sd = Sn / Sm
1897 return new FDivS(machInst, rd, rn, rm);
1898 case 0x11: // FDIV Dd = Dn / Dm
1899 return new FDivD(machInst, rd, rn, rm);
1900 case 0x02: // FADD Sd = Sn + Sm
1901 return new FAddS(machInst, rd, rn, rm);
1902 case 0x12: // FADD Dd = Dn + Dm
1903 return new FAddD(machInst, rd, rn, rm);
1904 case 0x03: // FSUB Sd = Sn - Sm
1905 return new FSubS(machInst, rd, rn, rm);
1906 case 0x13: // FSUB Dd = Dn - Dm
1907 return new FSubD(machInst, rd, rn, rm);
1908 case 0x04: // FMAX Sd = max(Sn, Sm)
1909 return new FMaxS(machInst, rd, rn, rm);
1910 case 0x14: // FMAX Dd = max(Dn, Dm)
1911 return new FMaxD(machInst, rd, rn, rm);
1912 case 0x05: // FMIN Sd = min(Sn, Sm)
1913 return new FMinS(machInst, rd, rn, rm);
1914 case 0x15: // FMIN Dd = min(Dn, Dm)
1915 return new FMinD(machInst, rd, rn, rm);
1916 case 0x06: // FMAXNM Sd = maxNum(Sn, Sm)
1917 return new FMaxNMS(machInst, rd, rn, rm);
1918 case 0x16: // FMAXNM Dd = maxNum(Dn, Dm)
1919 return new FMaxNMD(machInst, rd, rn, rm);
1920 case 0x07: // FMINNM Sd = minNum(Sn, Sm)
1921 return new FMinNMS(machInst, rd, rn, rm);
1922 case 0x17: // FMINNM Dd = minNum(Dn, Dm)
1923 return new FMinNMD(machInst, rd, rn, rm);
1924 case 0x08: // FNMUL Sd = -(Sn * Sm)
1925 return new FNMulS(machInst, rd, rn, rm);
1926 case 0x18: // FNMUL Dd = -(Dn * Dm)
1927 return new FNMulD(machInst, rd, rn, rm);
1928 default:
1929 return new Unknown64(machInst);
1930 }
1931 }
1932 case 0x3:
1933 {
1934 if (bits(machInst, 31) || bits(machInst, 29))
1935 return new Unknown64(machInst);
1936 uint8_t type = bits(machInst, 23, 22);
1937 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1938 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1939 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
1940 ConditionCode cond =
1941 (ConditionCode)(uint8_t)(bits(machInst, 15, 12));
1942 if (type == 0) // FCSEL Sd = if cond then Sn else Sm
1943 return new FCSelS(machInst, rd, rn, rm, cond);
1944 else if (type == 1) // FCSEL Dd = if cond then Dn else Dm
1945 return new FCSelD(machInst, rd, rn, rm, cond);
1946 else
1947 return new Unknown64(machInst);
1948 }
1949 }
1950 }
1951 return new FailUnimplemented("Unhandled Case4", machInst);
1952 }
1953}
1954}};
1955
1956output decoder {{
1957namespace Aarch64
1958{
1959 StaticInstPtr
1960 decodeAdvSIMDScalar(ExtMachInst machInst)
1961 {
1962 if (bits(machInst, 24) == 1) {
1963 if (bits(machInst, 10) == 0) {
1964 return decodeNeonScIndexedElem(machInst);
1965 } else if (bits(machInst, 23) == 0) {
1966 return decodeNeonScShiftByImm(machInst);
1967 }
1968 } else if (bits(machInst, 21) == 1) {
1969 if (bits(machInst, 10) == 1) {
1970 return decodeNeonSc3Same(machInst);
1971 } else if (bits(machInst, 11) == 0) {
1972 return decodeNeonSc3Diff(machInst);
1973 } else if (bits(machInst, 20, 17) == 0x0) {
1974 return decodeNeonSc2RegMisc(machInst);
1975 } else if (bits(machInst, 20, 17) == 0x8) {
1976 return decodeNeonScPwise(machInst);
1977 } else {
1978 return new Unknown64(machInst);
1979 }
1980 } else if (bits(machInst, 23, 22) == 0 &&
1981 bits(machInst, 15) == 0 &&
1982 bits(machInst, 10) == 1) {
1983 return decodeNeonScCopy(machInst);
1984 } else {
1985 return new Unknown64(machInst);
1986 }
1987 return new FailUnimplemented("Unhandled Case6", machInst);
1988 }
1989}
1990}};
1991
1992output decoder {{
1993namespace Aarch64
1994{
1995 template <typename DecoderFeatures>
1996 StaticInstPtr
1997 decodeFpAdvSIMD(ExtMachInst machInst)
1998 {
1999
2000 if (bits(machInst, 28) == 0) {
2001 if (bits(machInst, 31) == 0) {
2002 return decodeAdvSIMD<DecoderFeatures>(machInst);
2003 } else {
2004 return new Unknown64(machInst);
2005 }
2006 } else if (bits(machInst, 30) == 0) {
2007 return decodeFp(machInst);
2008 } else if (bits(machInst, 31) == 0) {
2009 return decodeAdvSIMDScalar(machInst);
2010 } else {
2011 return new Unknown64(machInst);
2012 }
2013 }
2014}
2015}};
2016
2017let {{
2018 decoder_output ='''
2019namespace Aarch64
2020{'''
2021 for decoderFlavour, type_dict in decoders.iteritems():
2022 decoder_output +='''
2023template StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst);
2024''' % { "df" : decoderFlavour }
2025 decoder_output +='''
2026}'''
2027}};
2028
2029output decoder {{
2030namespace Aarch64
2031{
2032 StaticInstPtr
2033 decodeGem5Ops(ExtMachInst machInst)
2034 {
2035 const uint32_t m5func = bits(machInst, 23, 16);
2036 switch (m5func) {
2037 case M5OP_ARM: return new Arm(machInst);
2038 case M5OP_QUIESCE: return new Quiesce(machInst);
2039 case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst);
2040 case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst);
2041 case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst);
2042 case M5OP_RPNS: return new Rpns64(machInst);
2043 case M5OP_WAKE_CPU: return new WakeCPU64(machInst);
2044 case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
2045 case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
2046 case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
2047 case M5OP_EXIT: return new M5exit64(machInst);
2048 case M5OP_FAIL: return new M5fail64(machInst);
2049 case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
2050 case M5OP_INIT_PARAM: return new Initparam64(machInst);
2051 case M5OP_RESET_STATS: return new Resetstats64(machInst);
2052 case M5OP_DUMP_STATS: return new Dumpstats64(machInst);
2053 case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst);
2054 case M5OP_CHECKPOINT: return new M5checkpoint64(machInst);
2055 case M5OP_WRITE_FILE: return new M5writefile64(machInst);
2056 case M5OP_READ_FILE: return new M5readfile64(machInst);
2057 case M5OP_DEBUG_BREAK: return new M5break(machInst);
2058 case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
2059 case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst);
2060 case M5OP_PANIC: return new M5panic(machInst);
2061 case M5OP_WORK_BEGIN: return new M5workbegin64(machInst);
2062 case M5OP_WORK_END: return new M5workend64(machInst);
2063 default: return new Unknown64(machInst);
2064 }
2065 }
2066}
2067}};
2068
2069def format Aarch64() {{
2070 decode_block = '''
2071 {
2072 using namespace Aarch64;
2073 if (bits(machInst, 27) == 0x0) {
2074 if (bits(machInst, 28) == 0x0)
2075 return new Unknown64(machInst);
2076 else if (bits(machInst, 26) == 0)
2077 // bit 28:26=100
2078 return decodeDataProcImm(machInst);
2079 else
2080 // bit 28:26=101
2081 return decodeBranchExcSys(machInst);
2082 } else if (bits(machInst, 25) == 0) {
2083 // bit 27=1, 25=0
2084 return decodeLoadsStores(machInst);
2085 } else if (bits(machInst, 26) == 0) {
2086 // bit 27:25=101
2087 return decodeDataProcReg(machInst);
2088 } else if (bits(machInst, 24) == 1 &&
2089 bits(machInst, 31, 28) == 0xF) {
2090 return decodeGem5Ops(machInst);
2091 } else {
2092 // bit 27:25=111
2093 switch(decoderFlavour){
2094 default:
2095 return decodeFpAdvSIMD<GenericDecoder>(machInst);
2096 }
2097 }
2098 }
2099 '''
2100}};