1// Copyright (c) 2011-2018 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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103 case 0x0:
104 return new AddXImm(machInst, rdsp, rnsp, imm);
105 case 0x1:
106 return new AddXImmCc(machInst, rdzr, rnsp, imm);
107 case 0x2:
108 return new SubXImm(machInst, rdsp, rnsp, imm);
109 case 0x3:
110 return new SubXImmCc(machInst, rdzr, rnsp, imm);
111 }
112 }
113 case 0x4:
114 {
115 if (!sf && n)
116 return new Unknown64(machInst);
117 // len = MSB(n:NOT(imms)), len < 1 is undefined.
118 uint8_t len = 0;

--- 26 unchanged lines hidden (view full) ---

145 case 0x0:
146 return new AndXImm(machInst, rdsp, rn, imm);
147 case 0x1:
148 return new OrrXImm(machInst, rdsp, rn, imm);
149 case 0x2:
150 return new EorXImm(machInst, rdsp, rn, imm);
151 case 0x3:
152 return new AndXImmCc(machInst, rdzr, rn, imm);
153 }
154 }
155 case 0x5:
156 {
157 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
158 IntRegIndex rdzr = makeZero(rd);
159 uint32_t imm16 = bits(machInst, 20, 5);
160 uint32_t hw = bits(machInst, 22, 21);
161 switch (opc) {
162 case 0x0:
163 return new Movn(machInst, rdzr, imm16, hw * 16);
164 case 0x1:
165 return new Unknown64(machInst);
166 case 0x2:
167 return new Movz(machInst, rdzr, imm16, hw * 16);
168 case 0x3:
169 return new Movk(machInst, rdzr, imm16, hw * 16);
170 }
171 }
172 case 0x6:
173 if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5))))
174 return new Unknown64(machInst);
175 switch (opc) {
176 case 0x0:
177 return new Sbfm64(machInst, rdzr, rn, immr, imms);
178 case 0x1:
179 return new Bfm64(machInst, rdzr, rn, immr, imms);
180 case 0x2:
181 return new Ubfm64(machInst, rdzr, rn, immr, imms);
182 case 0x3:
183 return new Unknown64(machInst);
184 }
185 case 0x7:
186 {
187 IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
188 if (opc || bits(machInst, 21))
189 return new Unknown64(machInst);
190 else
191 return new Extr64(machInst, rdzr, rn, rm, imms);

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400 return new FailUnimplemented(read ? "mrs" : "msr",
401 machInst,
402 csprintf("%s %s",
403 read ? "mrs" : "msr",
404 miscRegName[miscReg]));
405 }
406 }
407 break;
408 }
409 } else if (bits(machInst, 25) == 0x1) {
410 uint8_t opc = bits(machInst, 24, 21);
411 uint8_t op2 = bits(machInst, 20, 16);
412 uint8_t op3 = bits(machInst, 15, 10);
413 IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
414 uint8_t op4 = bits(machInst, 4, 0);
415 if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0)

--- 8 unchanged lines hidden (view full) ---

424 case 0x4:
425 if (rn != 0x1f)
426 return new Unknown64(machInst);
427 return new Eret64(machInst);
428 case 0x5:
429 if (rn != 0x1f)
430 return new Unknown64(machInst);
431 return new FailUnimplemented("dret", machInst);
432 }
433 }
434 default:
435 return new Unknown64(machInst);
436 }
437 return new FailUnimplemented("Unhandled Case7", machInst);
438 }
439}
440}};
441

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465 case 0x0:
466 return new STXRB64(machInst, rt, rnsp, rs);
467 case 0x1:
468 return new STXRH64(machInst, rt, rnsp, rs);
469 case 0x2:
470 return new STXRW64(machInst, rt, rnsp, rs);
471 case 0x3:
472 return new STXRX64(machInst, rt, rnsp, rs);
473 }
474 case 0x1:
475 switch (size) {
476 case 0x0:
477 return new STLXRB64(machInst, rt, rnsp, rs);
478 case 0x1:
479 return new STLXRH64(machInst, rt, rnsp, rs);
480 case 0x2:
481 return new STLXRW64(machInst, rt, rnsp, rs);
482 case 0x3:
483 return new STLXRX64(machInst, rt, rnsp, rs);
484 }
485 case 0x2:
486 switch (size) {
487 case 0x0:
488 case 0x1:
489 return new Unknown64(machInst);
490 case 0x2:
491 return new STXPW64(machInst, rs, rt, rt2, rnsp);
492 case 0x3:
493 return new STXPX64(machInst, rs, rt, rt2, rnsp);
494 }
495
496 case 0x3:
497 switch (size) {
498 case 0x0:
499 case 0x1:
500 return new Unknown64(machInst);
501 case 0x2:
502 return new STLXPW64(machInst, rs, rt, rt2, rnsp);
503 case 0x3:
504 return new STLXPX64(machInst, rs, rt, rt2, rnsp);
505 }
506
507 case 0x4:
508 switch (size) {
509 case 0x0:
510 return new LDXRB64(machInst, rt, rnsp, rs);
511 case 0x1:
512 return new LDXRH64(machInst, rt, rnsp, rs);
513 case 0x2:
514 return new LDXRW64(machInst, rt, rnsp, rs);
515 case 0x3:
516 return new LDXRX64(machInst, rt, rnsp, rs);
517 }
518 case 0x5:
519 switch (size) {
520 case 0x0:
521 return new LDAXRB64(machInst, rt, rnsp, rs);
522 case 0x1:
523 return new LDAXRH64(machInst, rt, rnsp, rs);
524 case 0x2:
525 return new LDAXRW64(machInst, rt, rnsp, rs);
526 case 0x3:
527 return new LDAXRX64(machInst, rt, rnsp, rs);
528 }
529 case 0x6:
530 switch (size) {
531 case 0x0:
532 case 0x1:
533 return new Unknown64(machInst);
534 case 0x2:
535 return new LDXPW64(machInst, rt, rt2, rnsp);
536 case 0x3:
537 return new LDXPX64(machInst, rt, rt2, rnsp);
538 }
539
540 case 0x7:
541 switch (size) {
542 case 0x0:
543 case 0x1:
544 return new Unknown64(machInst);
545 case 0x2:
546 return new LDAXPW64(machInst, rt, rt2, rnsp);
547 case 0x3:
548 return new LDAXPX64(machInst, rt, rt2, rnsp);
549 }
550
551 case 0x9:
552 switch (size) {
553 case 0x0:
554 return new STLRB64(machInst, rt, rnsp);
555 case 0x1:
556 return new STLRH64(machInst, rt, rnsp);
557 case 0x2:
558 return new STLRW64(machInst, rt, rnsp);
559 case 0x3:
560 return new STLRX64(machInst, rt, rnsp);
561 }
562 case 0xd:
563 switch (size) {
564 case 0x0:
565 return new LDARB64(machInst, rt, rnsp);
566 case 0x1:
567 return new LDARH64(machInst, rt, rnsp);
568 case 0x2:
569 return new LDARW64(machInst, rt, rnsp);
570 case 0x3:
571 return new LDARX64(machInst, rt, rnsp);
572 }
573 default:
574 return new Unknown64(machInst);
575 }
576 } else if (bits(machInst, 31)) {
577 return new Unknown64(machInst);
578 } else {
579 return decodeNeonMem(machInst);

--- 436 unchanged lines hidden (view full) ---

1016 case 0x1c:
1017 return new STRDFP64_PRE(machInst, rt, rnsp, imm);
1018 case 0x1d:
1019 return new LDRDFP64_PRE(machInst, rt, rnsp, imm);
1020 default:
1021 return new Unknown64(machInst);
1022 }
1023 }
1024 }
1025 }
1026 }
1027 }
1028 return new FailUnimplemented("Unhandled Case1", machInst);
1029 }
1030}
1031}};
1032
1033output decoder {{
1034namespace Aarch64

--- 30 unchanged lines hidden (view full) ---

1065 case 0x4:
1066 return new EorXSReg(machInst, rdzr, rn, rm, imm6, type);
1067 case 0x5:
1068 return new EonXSReg(machInst, rdzr, rn, rm, imm6, type);
1069 case 0x6:
1070 return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1071 case 0x7:
1072 return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1073 }
1074 }
1075 case 0x1:
1076 {
1077 uint8_t switchVal = bits(machInst, 30, 29);
1078 if (bits(machInst, 21) == 0) {
1079 ArmShiftType type =
1080 (ArmShiftType)(uint8_t)bits(machInst, 23, 22);

--- 10 unchanged lines hidden (view full) ---

1091 case 0x0:
1092 return new AddXSReg(machInst, rdzr, rn, rm, imm6, type);
1093 case 0x1:
1094 return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1095 case 0x2:
1096 return new SubXSReg(machInst, rdzr, rn, rm, imm6, type);
1097 case 0x3:
1098 return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
1099 }
1100 } else {
1101 if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4)
1102 return new Unknown64(machInst);
1103 ArmExtendType type =
1104 (ArmExtendType)(uint8_t)bits(machInst, 15, 13);
1105 uint8_t imm3 = bits(machInst, 12, 10);
1106 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);

--- 7 unchanged lines hidden (view full) ---

1114 case 0x0:
1115 return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3);
1116 case 0x1:
1117 return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
1118 case 0x2:
1119 return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3);
1120 case 0x3:
1121 return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
1122 }
1123 }
1124 }
1125 case 0x2:
1126 {
1127 if (bits(machInst, 21) == 1)
1128 return new Unknown64(machInst);
1129 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);

--- 10 unchanged lines hidden (view full) ---

1140 case 0x0:
1141 return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL);
1142 case 0x1:
1143 return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
1144 case 0x2:
1145 return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL);
1146 case 0x3:
1147 return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
1148 }
1149 }
1150 case 0x1:
1151 {
1152 if ((bits(machInst, 4) == 1) ||
1153 (bits(machInst, 10) == 1) ||
1154 (bits(machInst, 29) == 0)) {
1155 return new Unknown64(machInst);

--- 37 unchanged lines hidden (view full) ---

1193 case 0x0:
1194 return new Csel64(machInst, rdzr, rn, rm, cond);
1195 case 0x1:
1196 return new Csinc64(machInst, rdzr, rn, rm, cond);
1197 case 0x2:
1198 return new Csinv64(machInst, rdzr, rn, rm, cond);
1199 case 0x3:
1200 return new Csneg64(machInst, rdzr, rn, rm, cond);
1201 }
1202 }
1203 case 0x3:
1204 if (bits(machInst, 30) == 0) {
1205 if (bits(machInst, 29) != 0)
1206 return new Unknown64(machInst);
1207 uint8_t switchVal = bits(machInst, 15, 10);
1208 switch (switchVal) {

--- 47 unchanged lines hidden (view full) ---

1256 case 0x3:
1257 if (bits(machInst, 31) != 1)
1258 return new Unknown64(machInst);
1259 return new Rev64(machInst, rdzr, rn);
1260 case 0x4:
1261 return new Clz64(machInst, rdzr, rn);
1262 case 0x5:
1263 return new Cls64(machInst, rdzr, rn);
1264 }
1265 }
1266 }
1267 }
1268 case 0x3:
1269 {
1270 if (bits(machInst, 30, 29) != 0x0 ||
1271 (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0))
1272 return new Unknown64(machInst);
1273 IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);

--- 24 unchanged lines hidden (view full) ---

1298 case 0x6:
1299 if (bits(machInst, 15) != 0)
1300 return new Unknown64(machInst);
1301 return new Umulh64(machInst, rdzr, rn, rm);
1302 default:
1303 return new Unknown64(machInst);
1304 }
1305 }
1306 }
1307 return new FailUnimplemented("Unhandled Case2", machInst);
1308 }
1309}
1310}};
1311
1312output decoder {{
1313namespace Aarch64

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1479 return new FcvtFpUFixedDW(machInst, rd, rn, scale);
1480 case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits))
1481 return new FcvtFpUFixedSX(machInst, rd, rn, scale);
1482 case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits))
1483 return new FcvtFpUFixedDX(machInst, rd, rn, scale);
1484 default:
1485 return new Unknown64(machInst);
1486 }
1487 }
1488 } else {
1489 // 30=0, 28:24=11110, 21=1
1490 uint8_t type = bits(machInst, 23, 22);
1491 uint8_t imm8 = bits(machInst, 20, 13);
1492 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
1493 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
1494 switch (bits(machInst, 11, 10)) {

--- 446 unchanged lines hidden (view full) ---

1941 (ConditionCode)(uint8_t)(bits(machInst, 15, 12));
1942 if (type == 0) // FCSEL Sd = if cond then Sn else Sm
1943 return new FCSelS(machInst, rd, rn, rm, cond);
1944 else if (type == 1) // FCSEL Dd = if cond then Dn else Dm
1945 return new FCSelD(machInst, rd, rn, rm, cond);
1946 else
1947 return new Unknown64(machInst);
1948 }
1949 }
1950 }
1951 return new FailUnimplemented("Unhandled Case4", machInst);
1952 }
1953}
1954}};
1955
1956output decoder {{

--- 144 unchanged lines hidden ---