1// Copyright (c) 2011-2016 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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345 {
346 // bit 31:22=1101010100, 20:19=11
347 bool read = l;
348 MiscRegIndex miscReg =
349 decodeAArch64SysReg(op0, op1, crn, crm, op2);
350 if (read) {
351 if ((miscReg == MISCREG_DC_CIVAC_Xt) ||
352 (miscReg == MISCREG_DC_CVAC_Xt) ||
353 (miscReg == MISCREG_DC_ZVA_Xt)) {
354 return new Unknown64(machInst);
355 }
356 }
357 // Check for invalid registers
358 if (miscReg == MISCREG_UNKNOWN) {
359 return new Unknown64(machInst);
360 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
361 if (miscReg == MISCREG_NZCV) {
362 if (read)
363 return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg);
364 else
365 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt);
366 }
367 uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt);
368 if (miscReg == MISCREG_DC_ZVA_Xt && !read)
369 return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss);
370
371 if (read) {
372 StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss);
373 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
374 si->setFlag(StaticInst::IsUnverifiable);
375 return si;
376 } else {
377 return new Msr64(machInst, miscReg, rt, iss);
378 }
379 } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
380 std::string full_mnem = csprintf("%s %s",
381 read ? "mrs" : "msr", miscRegName[miscReg]);
382 return new WarnUnimplemented(read ? "mrs" : "msr",
383 machInst, full_mnem);
384 } else {
385 return new FailUnimplemented(read ? "mrs" : "msr",

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