1// Copyright (c) 2011-2014 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated

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41output header {{
42namespace Aarch64
43{
44 StaticInstPtr decodeDataProcImm(ExtMachInst machInst);
45 StaticInstPtr decodeBranchExcSys(ExtMachInst machInst);
46 StaticInstPtr decodeLoadsStores(ExtMachInst machInst);
47 StaticInstPtr decodeDataProcReg(ExtMachInst machInst);
48
49 StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst);
50 StaticInstPtr decodeFp(ExtMachInst machInst);
51 StaticInstPtr decodeAdvSIMD(ExtMachInst machInst);
52 StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst);
53
54 StaticInstPtr decodeGem5Ops(ExtMachInst machInst);
55}
56}};
57
58output decoder {{

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1273 return new FailUnimplemented("Unhandled Case2", machInst);
1274 }
1275}
1276}};
1277
1278output decoder {{
1279namespace Aarch64
1280{
1281 StaticInstPtr
1282 decodeAdvSIMD(ExtMachInst machInst)
1283 {
1284 if (bits(machInst, 24) == 1) {
1285 if (bits(machInst, 10) == 0) {
1286 return decodeNeonIndexedElem(machInst);
1287 } else if (bits(machInst, 23) == 1) {
1288 return new Unknown64(machInst);
1289 } else {
1290 if (bits(machInst, 22, 19)) {
1291 return decodeNeonShiftByImm(machInst);
1292 } else {
1293 return decodeNeonModImm(machInst);
1294 }
1295 }
1296 } else if (bits(machInst, 21) == 1) {
1297 if (bits(machInst, 10) == 1) {
1298 return decodeNeon3Same(machInst);
1299 } else if (bits(machInst, 11) == 0) {
1300 return decodeNeon3Diff(machInst);
1301 } else if (bits(machInst, 20, 17) == 0x0) {
1302 return decodeNeon2RegMisc(machInst);
1303 } else if (bits(machInst, 20, 17) == 0x8) {
1304 return decodeNeonAcrossLanes(machInst);
1305 } else {
1306 return new Unknown64(machInst);

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1952 return new FailUnimplemented("Unhandled Case6", machInst);
1953 }
1954}
1955}};
1956
1957output decoder {{
1958namespace Aarch64
1959{
1960 StaticInstPtr
1961 decodeFpAdvSIMD(ExtMachInst machInst)
1962 {
1963
1964 if (bits(machInst, 28) == 0) {
1965 if (bits(machInst, 31) == 0) {
1966 return decodeAdvSIMD(machInst);
1967 } else {
1968 return new Unknown64(machInst);
1969 }
1970 } else if (bits(machInst, 30) == 0) {
1971 return decodeFp(machInst);
1972 } else if (bits(machInst, 31) == 0) {
1973 return decodeAdvSIMDScalar(machInst);
1974 } else {
1975 return new Unknown64(machInst);
1976 }
1977 }
1978}
1979}};
1980
1981output decoder {{
1982namespace Aarch64
1983{
1984 StaticInstPtr
1985 decodeGem5Ops(ExtMachInst machInst)
1986 {
1987 const uint32_t m5func = bits(machInst, 23, 16);
1988 switch (m5func) {

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2036 } else if (bits(machInst, 26) == 0) {
2037 // bit 27:25=101
2038 return decodeDataProcReg(machInst);
2039 } else if (bits(machInst, 24) == 1 &&
2040 bits(machInst, 31, 28) == 0xF) {
2041 return decodeGem5Ops(machInst);
2042 } else {
2043 // bit 27:25=111
2044 return decodeFpAdvSIMD(machInst);
2045 }
2046 }
2047 '''
2048}};