1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2009 The Regents of The University of Michigan
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Gabe Black
42
431: decode BIGTHUMB {
44 // 16 bit thumb instructions.
45 0: decode TOPCODE_15_13 {
46 0x0, 0x1: Thumb16ShiftAddSubMoveCmp::thumb16ShiftAddMoveCmp();
47 0x2: decode TOPCODE_12_10 {
48 0x0: Thumb16DataProcessing::thumb16DataProcessing();
49 0x1: Thumb16SpecDataAndBx::thumb16SpecDataAndBx();
50 0x2, 0x3: Thumb16MemLit::thumb16MemLit();
51 default: Thumb16MemReg::thumb16MemReg();
52 }
53 0x3, 0x4: Thumb16MemImm::thumb16MemImm();
54 0x5: decode TOPCODE_12_11 {
55 0x0: Thumb16Adr::thumb16Adr();
56 0x1: Thumb16AddSp::thumb16AddSp(); //sp, immediate
57 0x2, 0x3: Thumb16Misc::thumb16Misc();
58 }
59 0x6: decode TOPCODE_12_11 {
60 0x0, 0x1: Thumb16MacroMem::thumb16MacroMem();
61 0x2, 0x3: Thumb16CondBranchAndSvc::thumb16CondBranchAndSvc();
62 }
63 0x7: decode TOPCODE_12_11 {
64 0x0: Thumb16UncondBranch::thumb16UncondBranch();
65 }
66 }
67
68 // 32 bit thumb instructions.
69 1: decode HTOPCODE_12_11 {
70 0x1: decode HTOPCODE_10_9 {
71 0x0: decode HTOPCODE_8_6 {
72 0x0, 0x6: decode HTOPCODE_4 {
73 0x0: WarnUnimpl::srs();
74 0x1: WarnUnimpl::rfe();
75 }
76 0x1: decode HTOPCODE_5_4 {
77 0x0: WarnUnimpl::strex();
78 0x1: WarnUnimpl::ldrex();
79 0x2: WarnUnimpl::strd(); // immediate
80 0x3: decode HTRN {
81 0xf: WarnUnimpl::ldrd(); // literal
82 default: WarnUnimpl::ldrd(); // immediate
83 }
84 }
85 // This uses the same encoding as regular ARM.
86 0x2: ArmMacroMem::armMacroMem();
87 0x3: decode HTOPCODE_5_4 {
88 0x0: decode LTOPCODE_7_4 {
89 0x4: WarnUnimpl::strexb();
90 0x5: WarnUnimpl::strexh();
91 0x7: WarnUnimpl::strexd();
92 }
93 0x1: decode LTOPCODE_7_4 {
94 0x0: WarnUnimpl::tbb();
95 0x1: WarnUnimpl::tbh();
96 0x4: WarnUnimpl::ldrexb();
97 0x5: WarnUnimpl::ldrexh();
98 0x7: WarnUnimpl::ldrexd();
99 }
100 0x2: WarnUnimpl::strd(); // immediate
101 0x3: decode HTRN {
102 0xf: WarnUnimpl::ldrd(); // literal
103 default: WarnUnimpl::ldrd(); // immediate
104 }
105 }
106 // This uses the same encoding as regular ARM.
107 0x4: ArmMacroMem::armMacroMem();
108 0x5, 0x7: decode HTOPCODE_4 {
109 0x0: WarnUnimpl::strd(); // immediate
110 0x1: decode HTRN {
111 0xf: WarnUnimpl::ldrd(); // literal
112 default: WarnUnimpl::ldrd(); // immediate
113 }
114 }
115 }
116 0x1: Thumb32DataProcShiftReg::thumb32DataProcShiftReg();
117 default: decode HTOPCODE_9_8 {
118 0x2: decode LTOPCODE_4 {
119 0x0: decode LTCOPROC {
120 0xa, 0xb: decode OPCODE_23_20 {
121##include "vfp.isa"
122 }
123 default: WarnUnimpl::cdp(); // cdp2
124 }
125 0x1: decode LTCOPROC {
126 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
127 default: decode HTOPCODE_4 {
128 0x0: WarnUnimpl::mcr(); // mcr2
129 0x1: WarnUnimpl::mrc(); // mrc2
130 }
131 }
132 }
133 0x3: WarnUnimpl::Advanced_SIMD();
134 default: decode LTCOPROC {
135 0xa, 0xb: decode HTOPCODE_9_4 {
136 0x00: WarnUnimpl::undefined();
137 0x04: WarnUnimpl::mcrr(); // mcrr2
138 0x05: WarnUnimpl::mrrc(); // mrrc2
139 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
140 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e:
141 WarnUnimpl::stc(); // stc2
142 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11,
143 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f:
144 decode HTRN {
145 0xf: WarnUnimpl::ldc(); // ldc2 (literal)
146 default: WarnUnimpl::ldc(); // ldc2 (immediate)
147 }
148 }
149 default: decode HTOPCODE_9_5 {
150 0x00: WarnUnimpl::undefined();
151 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
152 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
153 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
154 WarnUnimpl::Extension_register_load_store_instruction();
155 }
156 }
157 }
158 }
159 0x2: decode LTOPCODE_15 {
160 0x0: decode HTOPCODE_9 {
161 0x0: Thumb32DataProcModImm::thumb32DataProcModImm();
162 0x1: WarnUnimpl::Data_processing_plain_binary_immediate();
163 }
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2009 The Regents of The University of Michigan
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Gabe Black
42
431: decode BIGTHUMB {
44 // 16 bit thumb instructions.
45 0: decode TOPCODE_15_13 {
46 0x0, 0x1: Thumb16ShiftAddSubMoveCmp::thumb16ShiftAddMoveCmp();
47 0x2: decode TOPCODE_12_10 {
48 0x0: Thumb16DataProcessing::thumb16DataProcessing();
49 0x1: Thumb16SpecDataAndBx::thumb16SpecDataAndBx();
50 0x2, 0x3: Thumb16MemLit::thumb16MemLit();
51 default: Thumb16MemReg::thumb16MemReg();
52 }
53 0x3, 0x4: Thumb16MemImm::thumb16MemImm();
54 0x5: decode TOPCODE_12_11 {
55 0x0: Thumb16Adr::thumb16Adr();
56 0x1: Thumb16AddSp::thumb16AddSp(); //sp, immediate
57 0x2, 0x3: Thumb16Misc::thumb16Misc();
58 }
59 0x6: decode TOPCODE_12_11 {
60 0x0, 0x1: Thumb16MacroMem::thumb16MacroMem();
61 0x2, 0x3: Thumb16CondBranchAndSvc::thumb16CondBranchAndSvc();
62 }
63 0x7: decode TOPCODE_12_11 {
64 0x0: Thumb16UncondBranch::thumb16UncondBranch();
65 }
66 }
67
68 // 32 bit thumb instructions.
69 1: decode HTOPCODE_12_11 {
70 0x1: decode HTOPCODE_10_9 {
71 0x0: decode HTOPCODE_8_6 {
72 0x0, 0x6: decode HTOPCODE_4 {
73 0x0: WarnUnimpl::srs();
74 0x1: WarnUnimpl::rfe();
75 }
76 0x1: decode HTOPCODE_5_4 {
77 0x0: WarnUnimpl::strex();
78 0x1: WarnUnimpl::ldrex();
79 0x2: WarnUnimpl::strd(); // immediate
80 0x3: decode HTRN {
81 0xf: WarnUnimpl::ldrd(); // literal
82 default: WarnUnimpl::ldrd(); // immediate
83 }
84 }
85 // This uses the same encoding as regular ARM.
86 0x2: ArmMacroMem::armMacroMem();
87 0x3: decode HTOPCODE_5_4 {
88 0x0: decode LTOPCODE_7_4 {
89 0x4: WarnUnimpl::strexb();
90 0x5: WarnUnimpl::strexh();
91 0x7: WarnUnimpl::strexd();
92 }
93 0x1: decode LTOPCODE_7_4 {
94 0x0: WarnUnimpl::tbb();
95 0x1: WarnUnimpl::tbh();
96 0x4: WarnUnimpl::ldrexb();
97 0x5: WarnUnimpl::ldrexh();
98 0x7: WarnUnimpl::ldrexd();
99 }
100 0x2: WarnUnimpl::strd(); // immediate
101 0x3: decode HTRN {
102 0xf: WarnUnimpl::ldrd(); // literal
103 default: WarnUnimpl::ldrd(); // immediate
104 }
105 }
106 // This uses the same encoding as regular ARM.
107 0x4: ArmMacroMem::armMacroMem();
108 0x5, 0x7: decode HTOPCODE_4 {
109 0x0: WarnUnimpl::strd(); // immediate
110 0x1: decode HTRN {
111 0xf: WarnUnimpl::ldrd(); // literal
112 default: WarnUnimpl::ldrd(); // immediate
113 }
114 }
115 }
116 0x1: Thumb32DataProcShiftReg::thumb32DataProcShiftReg();
117 default: decode HTOPCODE_9_8 {
118 0x2: decode LTOPCODE_4 {
119 0x0: decode LTCOPROC {
120 0xa, 0xb: decode OPCODE_23_20 {
121##include "vfp.isa"
122 }
123 default: WarnUnimpl::cdp(); // cdp2
124 }
125 0x1: decode LTCOPROC {
126 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
127 default: decode HTOPCODE_4 {
128 0x0: WarnUnimpl::mcr(); // mcr2
129 0x1: WarnUnimpl::mrc(); // mrc2
130 }
131 }
132 }
133 0x3: WarnUnimpl::Advanced_SIMD();
134 default: decode LTCOPROC {
135 0xa, 0xb: decode HTOPCODE_9_4 {
136 0x00: WarnUnimpl::undefined();
137 0x04: WarnUnimpl::mcrr(); // mcrr2
138 0x05: WarnUnimpl::mrrc(); // mrrc2
139 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
140 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e:
141 WarnUnimpl::stc(); // stc2
142 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11,
143 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f:
144 decode HTRN {
145 0xf: WarnUnimpl::ldc(); // ldc2 (literal)
146 default: WarnUnimpl::ldc(); // ldc2 (immediate)
147 }
148 }
149 default: decode HTOPCODE_9_5 {
150 0x00: WarnUnimpl::undefined();
151 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
152 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
153 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
154 WarnUnimpl::Extension_register_load_store_instruction();
155 }
156 }
157 }
158 }
159 0x2: decode LTOPCODE_15 {
160 0x0: decode HTOPCODE_9 {
161 0x0: Thumb32DataProcModImm::thumb32DataProcModImm();
162 0x1: WarnUnimpl::Data_processing_plain_binary_immediate();
163 }
|
165 }
166 0x3: decode HTOPCODE_10_9 {
167 0x0: decode HTOPCODE_4 {
168 0x0: decode HTOPCODE_8 {
169 0x0: Thumb32StoreSingle::thumb32StoreSingle();
170 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store();
171 }
172 0x1: decode HTOPCODE_6_5 {
173 0x0: WarnUnimpl::Load_byte_memory_hints();
174 0x1: WarnUnimpl::Load_halfword_memory_hints();
175 0x2: Thumb32LoadWord::thumb32LoadWord();
176 0x3: WarnUnimpl::undefined();
177 }
178 }
179 0x1: decode HTOPCODE_8_7 {
180 0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference();
181 0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide();
182 default: WarnUnimpl::Data_processing_register();
183 }
184 default: decode HTOPCODE_9_8 {
185 0x2: decode LTOPCODE_4 {
186 0x0: decode LTCOPROC {
187 0xa, 0xb: WarnUnimpl::VFP_Inst();
188 default: WarnUnimpl::cdp(); // cdp2
189 }
190 0x1: decode LTCOPROC {
191 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
192 default: decode HTOPCODE_4 {
193 0x0: WarnUnimpl::mcr(); // mcr2
194 0x1: WarnUnimpl::mrc(); // mrc2
195 }
196 }
197 }
198 0x3: WarnUnimpl::Advanced_SIMD();
199 default: decode LTCOPROC {
200 0xa, 0xb: decode HTOPCODE_9_4 {
201 0x00: WarnUnimpl::undefined();
202 0x04: WarnUnimpl::mcrr(); // mcrr2
203 0x05: WarnUnimpl::mrrc(); // mrrc2
204 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
205 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e:
206 WarnUnimpl::stc(); // stc2
207 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11,
208 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f:
209 decode HTRN {
210 0xf: WarnUnimpl::ldc(); // ldc2 (literal)
211 default: WarnUnimpl::ldc(); // ldc2 (immediate)
212 }
213 }
214 default: decode HTOPCODE_9_5 {
215 0x00: WarnUnimpl::undefined();
216 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
217 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
218 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
219 WarnUnimpl::Extension_register_load_store_instruction();
220 }
221 }
222 }
223 }
224 }
225}
| 165 }
166 0x3: decode HTOPCODE_10_9 {
167 0x0: decode HTOPCODE_4 {
168 0x0: decode HTOPCODE_8 {
169 0x0: Thumb32StoreSingle::thumb32StoreSingle();
170 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store();
171 }
172 0x1: decode HTOPCODE_6_5 {
173 0x0: WarnUnimpl::Load_byte_memory_hints();
174 0x1: WarnUnimpl::Load_halfword_memory_hints();
175 0x2: Thumb32LoadWord::thumb32LoadWord();
176 0x3: WarnUnimpl::undefined();
177 }
178 }
179 0x1: decode HTOPCODE_8_7 {
180 0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference();
181 0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide();
182 default: WarnUnimpl::Data_processing_register();
183 }
184 default: decode HTOPCODE_9_8 {
185 0x2: decode LTOPCODE_4 {
186 0x0: decode LTCOPROC {
187 0xa, 0xb: WarnUnimpl::VFP_Inst();
188 default: WarnUnimpl::cdp(); // cdp2
189 }
190 0x1: decode LTCOPROC {
191 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
192 default: decode HTOPCODE_4 {
193 0x0: WarnUnimpl::mcr(); // mcr2
194 0x1: WarnUnimpl::mrc(); // mrc2
195 }
196 }
197 }
198 0x3: WarnUnimpl::Advanced_SIMD();
199 default: decode LTCOPROC {
200 0xa, 0xb: decode HTOPCODE_9_4 {
201 0x00: WarnUnimpl::undefined();
202 0x04: WarnUnimpl::mcrr(); // mcrr2
203 0x05: WarnUnimpl::mrrc(); // mrrc2
204 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
205 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e:
206 WarnUnimpl::stc(); // stc2
207 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11,
208 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f:
209 decode HTRN {
210 0xf: WarnUnimpl::ldc(); // ldc2 (literal)
211 default: WarnUnimpl::ldc(); // ldc2 (immediate)
212 }
213 }
214 default: decode HTOPCODE_9_5 {
215 0x00: WarnUnimpl::undefined();
216 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
217 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
218 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
219 WarnUnimpl::Extension_register_load_store_instruction();
220 }
221 }
222 }
223 }
224 }
225}
|